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ATF22V10CQ-15SI Datasheet(PDF) 6 Page - ATMEL Corporation

Part # ATF22V10CQ-15SI
Description  Highperformance EE PLD
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATF22V10CQ-15SI Datasheet(HTML) 6 Page - ATMEL Corporation

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ATF22V10C(Q)
0735P–PLD–01/02
Power-up Reset
The registers in the ATF22V10Cs are designed to reset during power-up. At a point
delayed slightly from VCC crossing VRST, all registers will be reset to the low state. The
output state will depend on the polarity of the output buffer.
This feature is critical for state machine initialization. However, due to the asynchronous
nature of reset and the uncertainty of how VCC actually rises in the system, the following
conditions are required:
1.
The V
CC rise must be monotonic, and starts below 0.7V,
2.
After reset occurs, all input and feedback setup times must be met before driving
the clock pin high, and
3.
The clock must remain stable during t
PR.
Preload of Registered
Outputs
The ATF22V10C’s registers are provided with circuitry to allow loading of each register
with either a high or a low. This feature will simplify testing since any state can be forced
into the registers to control test sequencing. A JEDEC file with preload is generated
when a source file with vectors is compiled. Once downloaded, the JEDEC file preload
sequence will be done automatically by most of the approved programmers after the
programming.
Electronic Signature
Word
There are 64 bits of programmable memory that are always available to the user, even if
the device is secured. These bits can be used for user-specific data.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF22V10C fuse pat-
terns. Once programmed, fuse verify and preload are inhibited. However, the 64-bit
User Signature remains accessible.
The security fuse should be programmed last, as its effect is immediate.
Programming/
Erasing
Programming/erasing is performed using standard PLD programmers. See “CMOS PLD
Programming Hardware & Software Support” for information on software/programming.
C
LOCK
VRST
POWER
REGISTERED
OUTPUTS
tS
t PR
t W
Parameter
Description
Typ
Max
Units
t
PR
Power-up Reset Time
600
1,000
ns
V
RST
Power-up Reset Voltage
3.8
4.5
V


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