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ADN2811 Datasheet(PDF) 3 Page - Analog Devices

Part No. ADN2811
Description  OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADN2811 Datasheet(HTML) 3 Page - Analog Devices

 
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REV. A
ADN2811
–3–
Parameter
Conditions
Min
Typ
Max
Unit
CML OUTPUTS (CLKOUTP/N, DATAOUTP/N)
Single-Ended Output Swing
VSE (See Figure 3)
300
455
600
mV
Differential Output Swing
VDIFF (See Figure 3)
600
910
1200
mV
Output High Voltage
VOH
VCC
V
Output Low Voltage
VOL
VCC – 0.6
VCC – 0.3
V
Rise Time
20%–80%
84
150
ps
Fall time
80%–20%
84
150
ps
Setup Time
TS (See Figure 1)
OC-48
140
ps
Hold Time
TH (See Figure 1)
OC-48
150
ps
REFCLK DC INPUT CHARACTERISTICS
Input Voltage Range
@ REFCLKP or REFCLKN
0
VCC
V
Peak-to-Peak Differential Input
100
mV
Common-Mode Level
DC-Coupled, Single-Ended
VCC/2
V
TEST DATA DC INPUT
CHARACTERISTICS
4 (TDINP/N)
CML Inputs
Peak-to-Peak Differential Input Voltage
0.8
V
LVTTL DC INPUT CHARACTERISTICS
Input High Voltage
VIH
2.0
V
Input Low Voltage
VIL
0.8
V
Input Current
VIN = 0.4 V or VIN = 2.4 V
–5
+5
LVTTL DC OUTPUT CHARACTERISTICS
Output High Voltage
VOH, IOH = –2.0 mA
2.4
V
Output Low Voltage
VOL, IOL = +2.0 mA
0.4
V
NOTES
1PIN and NIN should be differentially driven, ac-coupled for optimum sensitivity.
2PWD measurement made on quantizer outputs in BYPASS mode.
3Measurement is equipment limited.
4TDINP/N are CML inputs. If the drivers to the TDINP/N inputs are anything other than CML, they must be ac-coupled.
Specifications subject to change without notice.


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