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ADN2811 Datasheet(PDF) 5 Page - Analog Devices

Part No. ADN2811
Description  OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADN2811 Datasheet(HTML) 5 Page - Analog Devices

 
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REV. A
ADN2811
–5–
PIN CONFIGURATION
PIN 1
INDICATOR
TOP VIEW
ADN2811
THRADJ 1
VCC 2
VEE 3
VREF 4
PIN 5
NIN 6
SLICEP 7
SLICEN 8
VEE 9
LOL 10
XO1 11
XO2 12
36 VCC
35 VCC
34 VEE
33 VEE
32 NC
31 NC
30 RATE
29 VEE
28 VCC
27 VEE
26 VCC
25 CF2
NC = NO CONNECT
PIN FUNCTION DESCRIPTION
Pin No.
Mnemonic
Type
Description
1
THRADJ
AI
LOS Threshold Setting Resistor
2, 26, 28, Pad
VCC
P
Analog Supply
3, 9, 16, 19, 22, 27, 29,
VEE
P
Ground
33, 34, 42, 43, 46
4
VREF
AO
Internal VREF Voltage. Decouple to GND with 0.1
µF capacitor.
5
PIN
AI
Differential Data Input. CML.
6NIN
AI
Differential Data Input. CML.
7
SLICEP
AI
Differential Slice Level Adjust Input
8
SLICEN
AI
Differential Slice Level Adjust Input
10
LOL
DO
Loss of Lock Indicator. LVTTL active high.
11
XO1
AO
Crystal Oscillator
12
XO2
AO
Crystal Oscillator
13
REFCLKN
DI
Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS
(LVPECL, LVDS only at 155.52 MHz).
14
REFCLKP
DI
Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS
(LVPECL, LVDS only at 155.52 MHz).
15
REFSEL
DI
Reference Source Select. “0” = on-chip oscillator with external crystal;
“1” = external clock source, LVTTL.
17
TDINP
AI
Differential Test Data Input
18
TDINN
AI
Differential Test Data Input
20, 47
VCC
P
Digital Supply
21
CF1
AO
Frequency Loop Capacitor
23
REFSEL1
DI
Reference Frequency Select (See Table II) LVTTL.
24
REFSEL0
DI
Reference Frequency Select (See Table II) LVTTL.
25
CF2
AO
Frequency Loop Capacitor
30
RATE
DI
Data Rate Select (See Table I) LVTTL.
31, 32
NC
DI
No Connect
35, 36
VCC
P
Output Driver Supply
37
DATAOUTN
DO
Differential Retimed Data Output. CML.
38
DATAOUTP
DO
Differential Retimed Data Output. CML.
39
SQUELCH
DI
Disable Clock and Data Outputs. Active high. LVTTL.
40
CLKOUTN
DO
Differential Recovered Clock Output. CML.
41
CLKOUTP
DO
Differential Recovered Clock Output. CML.
44
BYPASS
DI
Bypass CDR Mode. Active high. LVTTL.
45
SDOUT
DO
Loss of Signal Detect Output. Active high. LVTTL.
48
LOOPEN
DI
Enable Test Data Inputs. Active high. LVTTL.
Type: P = Power, AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output


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