AD5339 datasheet(19/24 Pages) AD

Part #	AD5339

Description	2.5 V to 5.5 V, 250 UA, 2-Wire Interface Dual-Voltage Output, 8-/10-/12-Bit DACs

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AD5337/AD5338/AD5339

Rev. A | Page 19 of 24

DOUBLE-BUFFERED INTERFACE

The AD5337/AD5338/AD5339 DACs all have a double-buffered

interface consisting of two banks of registers—an input register

and a DAC register per channel. The input register is directly

connected to the input shift register, and the digital code is

transferred to the relevant input register upon completion of a

valid write sequence. The DAC register contains the digital code

used by the resistor string.

Access to the DAC register is controlled by the LDAC bit. When

the LDAC bit is set high, the DAC register is latched and therefore

the input register may change state without affecting the DAC

register. This is useful if the user requires simultaneous updating

of all DAC outputs. The user may write to three of the input

registers individually; by setting the LDAC bit low when writing

to the remaining DAC input register, all outputs will update

simultaneously.

These parts contain an extra feature whereby the DAC register

is only updated if its input register has been updated since the

last time that LDAC was brought low, thereby removing

unnecessary digital crosstalk.

POWER-DOWN MODES

The AD5337/AD5338/AD5339 have very low power

consumption, typically dissipating 0.75 mW with a 3 V supply

and 1.5 mW with a 5 V supply. Power consumption can be

further reduced when the DACs are not in use by putting them

into one of three power-down modes, which are selected by

Bits 15 and 14 (PD1 and PD0) of the data byte. Table 8 shows

how the state of the bits corresponds to the mode of operation

of the DAC.

Table 8. PD1/PD0 Operating Modes

PD1

PD0

Operating Mode

0

Normal Operation

0

1

Power-Down (1 kΩ Load to GND)

1

0

Power-Down (100 kΩ Load to GND)

1

Power-Down (3-State Output)

When both bits are 0, the DAC works with its normal power

consumption of 300 µA at 5 V. However, for the three power-

down modes, the supply current falls to 200 nA at 5 V (80 nA at

3 V). Not only does the supply current drop, but the output

stage is also internally switched from the output of the amplifier

to a resistor network of known values. This is advantageous in

that the output impedance of the part is known while the part is

in power-down mode, which provides a defined input condition

for whatever is connected to the output of the DAC amplifier.

There are three options. The output may be connected internally

to GND through a 1 kΩ resistor, a 100 kΩ resistor, or may be

left open-circuited (3-state). Resistor tolerance = ±20%. The

output stage is illustrated in Figure 35.

AMPLIFIER

POWER-DOWN

CIRCUITRY

RESISTOR

NETWORK

RESISTOR

STRING DAC

VOUT

Figure 35. Output Stage during Power-Down

The bias generator, the output amplifiers, the resistor string, and

all other associated linear circuitry are shut down when power-

down mode is activated. However, the contents of the DAC

registers remain unchanged when power-down mode is activated.

The time to exit power-down is typically 2.5 µs for VDD = 5 V

and 5 µs when VDD = 3 V. This is the time from the rising edge

of the eighth SCL pulse to the time when the output voltage

deviates from its power-down voltage. See Figure 23 for a plot.

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