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AD5273 Datasheet(PDF) 12 Page - Analog Devices

Part No. AD5273
Description  64-Position OTP Digital Potentiometer
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5273 Datasheet(HTML) 12 Page - Analog Devices

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AD5273
–12–
Note that in the zero-scale condition a finite wiper resistance of
60
is present. Care should be taken to limit the current flow
between W and B in this state to a maximum pulse current of no
more than 20 mA. Otherwise, degradation or possible destruction
of the internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper W and terminal A also produces a
digitally controlled complementary resistance RWA. When these
terminals are used, terminal B can be opened. Setting the resis-
tance value for RWA starts at a maximum value of resistance and
decreases as the data loaded in the latch increases in value. The
general equation for this operation is:
RD
D
RR
WA
AB
W
() =¥ +
63
63
(2)
For RAB = 10 k and terminal B is opened, the following output
resistance RWA will be set for the following RDAC latch codes.
D (DEC)
R WA ( )
Output State
63
60
Full-Scale
32
4980
Midscale
1
9901
1 LSB
0
10060
Zero-Scale
The typical distribution of the nominal resistance RAB from channel
to channel matches within ±1%. Device-to-device matching is
process lot dependent and is possible to have ±30% variation.
D5
D4
D3
D2
D1
D0
RDAC
LATCH
AND
DECODER
RS
RS
RS
A
W
B
Figure 3. Equivalent RDAC Circuit
Voltage Output Operation
Similar to the D/A converter, the digital potentiometer easily
generates a voltage divider at wiper-to-B and wiper-to-A to be
proportional to the input voltage at A–B. Unlike the polarity of
VDD, which must be positive, voltage across A–B, W–A, and W–B
can be at either polarity as long as the voltage across them is <
IVDDI.
If ignoring the effect of the wiper resistance for approximation,
connecting terminal A to 5 V and terminal B to ground produces
an output voltage at the wiper-to-B starting at 0 V up to 5 V. Each
LSB of voltage is equal to the voltage applied across terminal A–B,
divided by the 63 position of the potentiometer divider as:
VD
D
V
WA
() =
63
(3)
For a more accurate calculation, which includes the effect of
wiper resistance, VW can be found as:
VD
RD
R
V
W
WB
AB
A
() =
()
(4)
Operation of the digital potentiometer in the divider mode results
in a more accurate operation overtemperature. Unlike the rheostat
mode, the output voltage is dependent mainly on the ratio of the
internal resistors RWA and RWB and not the absolute values, there-
fore, the temperature drift reduces to 10 ppm/°C.
ESD PROTECTION
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures shown in Figures 4a and 4b. This
applies to digital input pins SDA and SCL.
LOGIC
340
Figure 4a. ESD Protection of Digital Pins
A,B,W
Figure 4b. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The VDD of AD5273 defines the boundary conditions for proper
3-terminal digital potentiometer operation. Supply signals present
on terminals A, B, and W that exceed VDD will be clamped by the
internal forward-biased diodes. See Figure 5.
GND
A
W
B
VDD
Figure 5. Maximum Terminal Voltages Set by VDD
POWER-UP SEQUENCE
Since there are ESD protection diodes that limit the voltage compli-
ance at terminals A, B, and W (Figure 5), it is important to power
VDD first before applying any voltage to terminals A, B, and W.
Otherwise, the diode will be forward-biased such that VDD will
be powered unintentionally and may affect the rest of the users’
circuits. The ideal power-up sequence is in the following order:
GND, VDD, digital inputs, and VA/B/W. The order of powering VA,
VB, VW, and digital inputs is not important as long as they are
powered after VDD.
POWER SUPPLY CONSIDERATIONS
AD5273 employs fuse link technology, which requires an adequate
current density to blow the internal fuses to achieve a given setting.
As a result, the power supply, either an on-board linear regulator
or rack-mount power supply, must be rated at 5 V with less than
±5% tolerance. The supply should be able to handle 100 mA of
transient current, and lasts about 400 ms, during the one-time
programming. A low ESR 1 µF to 10 µF tantalum or electrolytic
REV. 0


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