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75N43102 Datasheet(PDF) 2 Page - Integrated Device Technology

Part # 75N43102
Description  NETWORK SEARCH ENGINE 32K x 72 Entries
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

75N43102 Datasheet(HTML) 2 Page - Integrated Device Technology

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Datasheet Brief 75N43102
Registers
There are three basic types of registers supported:
s Configuration Registers are used at initialization to define the
segmentation of the entries.
s Global Mask Registers are provided to support Lookup
instructions by masking individual bits during a search.
s Reply Width Registers are used with Lookup operations.
Functional Highlights
Figure 1.1
Bus Interface
The NSE utilizes a dual bus interface consisting of the NSE Request
Bus and the NSE Response Bus.
The NSE Request Bus is comprised of the Command Bus and the
RequestDataBus. TheCommandBushandlestheinstructiontotheNSE
while the Request Data Bus is the main data path to the NSE.
The72bitbi-directionalRequestDataBusfunctionsasamultiplexed
address and data bus, which performs the writing and reading of NSE
entries, as well as presenting lookup data to the device.
The NSE Response Bus is comprised of an independent unidirec-
tionalIndexBuswhichdrivestheresultofthelookup(orindex) to anASIC.
Data and Mask Array
The NSE has Data cell entries and associ-
atedMaskcellentriesasshowninFig.1.1. This
combination of Data and Mask cell entries en-
ables the NSE to store 0, 1 or X, making it a full
ternary Network Search Engine. During a
lookup operation, both arrays are used along
with a Global Mask Register to find a match to a
requested data word.
A 6435 drw 03
Dat a
Mask
Command Bus
TheCommandBusloadsthe specificinstructionsintotheNSE.These
include:
s
Read or Write
A Read or Write instruction operates on a specified data entry, mask
entry, or register.
s
Lookup
A lookup can be requested in 72-bit, 144-bit or 288-bit widths. A 36-
bit lookup can be accomplished by using two Global Mask Registers.
Features
s
s
s
s
s
Full Ternary 32K x 72 bit content addressable memory
s
s
s
s
s
Global Mask Registers
s
s
s
s
s
72/144/288 multiple width lookups
s
s
s
s
s
62.5M sustained lookups per second at 72 and 144 width lookups
s
s
s
s
s
Dual bus interface
s
s
s
s
s
Cascadable to 2 devices with no glue logic or latency penalty
s
s
s
s
s
Boundary Scan JTAG Interface (IEEE 1149.1compliant)
s
s
s
s
s
1.5V match power supply
s
s
s
s
s
2.5V core and I/O power supply


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