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MRF24XA Datasheet(PDF) 69 Page - Microchip Technology |
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MRF24XA Datasheet(HTML) 69 Page - Microchip Technology |
69 / 258 page 2015 Microchip Technology Inc. Preliminary DS70005023C-page 69 MRF24XA REGISTER 2-60: SFD6 (START FRAME DELIMITER PATTERN 6 CONFIGURATION REGISTER) ADDRESS: 0x65 REGISTER 2-61: SFD7 (START FRAME DELIMITER PATTERN 7 CONFIGURATION REGISTER) ADDRESS: 0x66 R/W-10101000 SFD6<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown r = Reserved bit 7-0 SFD6<7:0>: Start Frame Delimiter Pattern 6 Register Field bits When OPTIMAL = 1: This octet is used as the LSB of the SFD pattern with 2 Mbps rate. This octet is used as the LSB of the SFD pattern with 125 kbps rate. When OPTIMAL = 0: The value 0xA7 is forbidden.The hexadecimal digits must be different from 0x0 and different from the corresponding digits in SFD<k>, k = 4 or 1, 2, 3. R/W-11001000 SFD7<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown r = Reserved bit 7-0 SFD7<7:0>: Start Frame Delimiter Pattern 7 Register Field bits When OPTIMAL = 1, this octet is used as the LSB of the SFD pattern with 1 Mbps rate. |
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