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AMIC120 Datasheet(PDF) 3 Page - Texas Instruments |
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AMIC120 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 239 page 3 AMIC120 www.ti.com SPRSP09 – DECEMBER 2017 Submit Documentation Feedback Product Folder Links: AMIC120 Device Overview Copyright © 2017, Texas Instruments Incorporated 2.0 Specifications – Up to Three I2C Master and Slave Interfaces – Standard Mode (up to 100 kHz) – Fast Mode (up to 400 kHz) – Up to Six Banks of General-Purpose I/O (GPIO) – 32 GPIOs per Bank (Multiplexed With Other Functional Pins) – GPIOs Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank) – Up to Three External DMA Event Inputs That Can Also be Used as Interrupt Inputs – Twelve 32-Bit General-Purpose Timers – DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks – DMTIMER4–DMTIMER7 are Pinned Out – One Public Watchdog Timer – One Free-Running, High-Resolution 32-kHz Counter (synctimer32K) – Two 12-Bit SAR ADCs (ADC0, ADC1) – 867K Samples Per Second – Input Can Be Selected from Any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch – Up to Three 32-Bit eCAP Modules – Configurable as Three Capture Inputs or Three Auxiliary PWM Outputs – Up to Six Enhanced eHRPWM Modules – Dedicated 16-Bit Time-Base Counter With Time and Frequency Controls – Configurable as Six Single-Ended, Six Dual- Edge Symmetric, or Three Dual-Edge Asymmetric Outputs – Up to Three 32-Bit eQEP Modules • Device Identification – Factory Programmable Electrical Fuse Farm (FuseFarm) – Production ID – Device Part Number (Unique JTAG ID) – Device Revision (Readable by Host ARM) • Debug Interface Support – JTAG and cJTAG for ARM (Cortex-A9 and PRCM) and PRU-ICSS Debug – Supports Real-Time Trace Pins (for Cortex-A9) – 64-KB Embedded Trace Buffer (ETB) – Supports Device Boundary Scan – Supports IEEE 1500 • DMA – On-Chip Enhanced DMA Controller (EDMA) Has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels – EDMA is Used for: – Transfers to and from On-Chip Memories – Transfers to and from External Storage (EMIF, GPMC, and Slave Peripherals) • InterProcessor Communication (IPC) – Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between the Cortex-A9, PRCM, and PRU-ICSS • Boot Modes – Boot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin • Package – 491-Pin BGA Package (17-mm × 17-mm) (ZDN Suffix), 0.65-mm Ball Pitch With Via Channel Array Technology to Enable Low-Cost Routing 1.2 Applications • Industrial Communications • Connected Industrial Drives • Backplane I/O |
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