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ADS7142IRUGR Datasheet(PDF) 10 Page - Texas Instruments |
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ADS7142IRUGR Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 74 page  tf tr tSU-DAT tHD-DAT tVD-DAT « cont. « cont. 9 th clock SDA SCL 70% 30% 70% 30% 70% 30% 30% 70% 70% 30% 70% 30% tHIGH tLOW tHD-STA S 1/fSCL 1 st clock cycle . . . SDA . . . SCL tr tSU-STA tHD-STA Sr tSP tVD-ACK 70% 30% 9 th clock tBUF S P tSU-STO VIL = 0.3VDD VIH = 0.7VDD tf 10 ADS7142 SBAS773A – SEPTEMBER 2017 – REVISED DECEMBER 2017 www.ti.com Product Folder Links: ADS7142 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Switching Characteristics (continued) At TA = -40°C to 125°C, AVDD = 3V, DVDD = 1.65 to 3.6V, All Channel Configurations, unless otherwise noted. (1) PARAMETER Test Conditions MIN MAX UNIT trCL1 Rise time of SCLH after a repeated start condition and after an acknowledge bit 20 160 ns trDA Rise time of SDAH 20 160 ns tfCL Fall time of SCLH 20 80 ns tfDA Fall time of SDAH 20 160 ns tSP pulse width of spikes suppressed by the input filter 0 10 ns High Speed mode (3.4 MHz) Cb = 100 pF (Max) Figure 2 trCL Rise time of SCLH 10 40 ns trCL1 Rise time of SCLH after a repeated start condition and after an acknowledge bit 10 80 ns trDA Rise time of SDAH 10 80 ns tfCL Fall time of SCLH 10 40 ns tfDA Fall time of SDAH 10 80 ns tSP pulse width of spikes suppressed by the input filter 0 10 ns Figure 1. Timing Diagram for Standard-mode, Fast-mode and Fast-mode Plus |
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