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ADS7052 Datasheet(PDF) 23 Page - Texas Instruments |
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ADS7052 Datasheet(HTML) 23 Page - Texas Instruments |
23 / 44 page Sample A Sample A+1 tCYCLE 1 2 3 16 0 D13 Data Output for Sample A-1 0 tACQ 0 64 D0 D12 4 17 SCLK SDO CS 23 ADS7052 www.ti.com SBAS858 – DECEMBER 2017 Product Folder Links: ADS7052 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) In addition to the timing specifications of Figure 39 and Table 4, the timing specifications described in Figure 2 and the Timing Requirements table are also applicable for offset calibration during normal operation. 8.4.3.2 Offset Calibration During Normal Operation During normal operation, the host must provide 64 SCLKs in the serial transfer frame to enter the OFFCAL state. The device provides the conversion result for the previous sample during the first 18 SCLKs and 0's on SDO for the rest of the SCLKs in the serial transfer frame. For acquisition of the next sample, a minimum time of tACQ must be provided. If the host controller provides more than 18 SCLKs but pulls the CS high before providing 64 SCLKs, then the offset calibration process is aborted and the device enters the ACQ state. Figure 39 and Table 4 provide the timing for offset calibration during normal operation. Figure 39. Timing for Offset Calibration During Normal Operation Table 4. Timing Specifications for Offset Calibration During Normal Operation(1) MIN TYP MAX UNIT tcycle Cycle time for offset calibration on power-up 64 × tCLK + tACQ ns tACQ Acquisition time 230 ns fSCLK Frequency of SCLK 24 MHz |
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