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ADS7046 Datasheet(PDF) 15 Page - Texas Instruments |
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ADS7046 Datasheet(HTML) 15 Page - Texas Instruments |
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15 / 44 page  CDAC Comparator SAR Serial Interface Offset Calibration AINP AINM AVDD DVDD GND CS SCLK SDO 15 ADS7046 www.ti.com SBAS785 – DECEMBER 2016 Product Folder Links: ADS7046 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 8 Detailed Description 8.1 Overview The ADS7046 device belongs to a family of pin-to-pin compatible, high-speed, low-power, single-channel successive-approximation register (SAR) type analog-to-digital converters (ADCs). The device family includes multiple resolutions, throughputs, and analog input variants (see Table 1 for a list of devices). The ADS7046 is a 12-bit, 3-MSPS SAR ADC that supports a single-ended input in the range of 0 V to AVDD, for AVDD in the range of 2.35 V to 3.6 V (see the Analog Input section for details on the analog input pins). The internal offset calibration feature (see the OFFCAL State section) maintains excellent offset specifications over the entire AVDD and temperature operating range. The device supports an SPI-compatible serial interface that is controlled by the CS and SCLK signals. The input signal is sampled with the CS falling edge and SCLK is used for both, conversion and serial data output (see the Device Functional Modes section, Timing Requirements table, and Switching Characteristics table). The device supports a wide digital supply range (1.65 V to 3.6 V), enabling direct interfacing to a variety of host controllers. The ADS7046 complies with the JESD8-7A standard (see the Digital Voltage Levels section) for a normal DVDD range (1.65 V to 1.95 V). The ADS7046 is available in an 8-pin, small, X2QFN package (see the Mechanical, Packaging, and Orderable Information section for more details) and is specified over the extended industrial temperature range (–40°C to +125°C). The small form-factor and extremely-low power consumption make this device suitable for space-constrained and battery-powered applications that require high-speed, high-resolution data acquisition (see the Application Information section). 8.2 Functional Block Diagram |
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