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ADC12DJ2700 Datasheet(PDF) 100 Page - Texas Instruments

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Part No. ADC12DJ2700
Description  5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12DJ2700 Datasheet(HTML) 100 Page - Texas Instruments

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ADC12DJ2700
SLVSEH9 – JANUARY 2018
www.ti.com
Product Folder Links: ADC12DJ2700
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
7.6.1.5.24
Timing Adjust for B-ADC, Dual-Channel Mode Register (address = 0x089) [reset = Undefined]
Figure 126. Timing Adjust for B-ADC, Dual-Channel Mode Register (TADJ_B)
7
6
5
4
3
2
1
0
TADJ_B
R/W
Table 88. TADJ_B Field Descriptions
Bit
Field
Type
Reset
Description
7-0
TADJ_B
R/W
Undefined
This register (and other subsequent TADJ* registers) are used
to adjust the sampling instant of each ADC core. Different TADJ
registers apply to different ADCs under different modes or
phases of background calibration. After reset, the factory-
trimmed value can be read and adjusted as required.
7.6.1.5.25
Offset Adjustment for A-ADC and INA Register (address = 0x08A-0x08B) [reset = Undefined]
Figure 127. Offset Adjustment for A-ADC and INA Register (OADJ_A_INA)
15
14
13
12
11
10
9
8
RESERVED
OADJ_A_INA[11:8]
R/W-0000
R/W
7
6
5
4
3
2
1
0
OADJ_A_INA[7:0]
R/W
Table 89. OADJ_A_INA Field Descriptions
Bit
Field
Type
Reset
Description
15-12
RESERVED
R/W
0000
RESERVED
11-0
OADJ_A_INA
R/W
Undefined
Offset adjustment value for ADC0 (A-ADC) applied when ADC0
samples INA. The format is unsigned. After reset, the factory-
trimmed value can be read and adjusted as required.
Important notes:
Never write OADJ* registers while foreground calibration is
underway
Never write OADJ* registers if CAL_BG and CAL_BGOS
are set
If CAL_OS = 1 and CAL_BGOS = 0, only read OADJ*
registers if FG_DONE = 1
If CAL_BG = 1 and CAL_BGOS = 1, only read OADJ*
register if CAL_STOPPED = 1


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