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ADC12DJ2700 Datasheet(PDF) 94 Page - Texas Instruments

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Part No. ADC12DJ2700
Description  5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12DJ2700 Datasheet(HTML) 94 Page - Texas Instruments

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94
ADC12DJ2700
SLVSEH9 – JANUARY 2018
www.ti.com
Product Folder Links: ADC12DJ2700
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
7.6.1.5.7
Low-Power Background Calibration Register (address = 0x06E) [reset = 0x88]
Figure 109. Low-Power Background Calibration Register (CAL_LP)
7
6
5
4
3
2
1
0
LP_SLEEP_DLY
LP_WAKE_DLY
RESERVED
LP_TRIG
LP_EN
R/W-010
R/W-01
R/W-0
R/W-0
R/W-0
Table 71. CAL_LP Field Descriptions
Bit
Field
Type
Reset
Description
7-5
LP_SLEEP_DLY
R/W
010
Adjust how long an ADC sleeps before waking up for calibration
(only applies when LP_EN = 1 and LP_TRIG = 0). Values below
4 are not recommended because of limited overall power
reduction benefits.
0: Sleep delay = (23 + 1) × 256 × tDEVCLK
1: Sleep delay = (215 + 1) × 256 × tDEVCLK
2: Sleep delay = (218 + 1) × 256 × tDEVCLK
3: Sleep delay = (221 + 1) × 256 × tDEVCLK
4: Sleep delay = (224 + 1) × 256 × tDEVCLK : default is
approximately 1338 ms with a 3.2-GHz clock
5: Sleep delay = (227 + 1) × 256 × tDEVCLK
6: Sleep delay = (230 + 1) × 256 × tDEVCLK
7: Sleep delay = (233 + 1) × 256 × tDEVCLK
4-3
LP_WAKE_DLY
R/W
01
Adjust how much time is given up for settling before calibrating
an ADC after wake-up (only applies when LP_EN = 1). Values
lower than 1 are not recommended because there is insufficient
time for the core to stabilize before calibration begins.
0:Wake Delay = (23 + 1) × 256 × tDEVCLK
1: Wake Delay = (218 + 1) × 256 × tDEVCLK : default is
approximately 21 ms with a 3.2-GHz clock
2: Wake Delay = (221 + 1) × 256 × tDEVCLK
3: Wake Delay = (224 + 1) × 256 × tDEVCLK
2
RESERVED
R/W
0
RESERVED
1
LP_TRIG
R/W
0
0: ADC sleep duration is set by LP_SLEEP_DLY (autonomous
mode)
1: ADCs sleep until woken by a trigger; an ADC is awoken when
the calibration trigger (CAL_SOFT_TRIG bit or CAL_TRIG input)
is low
0
LP_EN
R/W
0
0: Disables low-power background calibration (default)
1: Enables low-power background calibration (only applies when
CAL_BG = 1)
7.6.1.5.8
Calibration Data Enable Register (address = 0x070) [reset = 0x00]
Figure 110. Calibration Data Enable Register (CAL_DATA_EN)
7
6
5
4
3
2
1
0
RESERVED
CAL_DATA_EN
R/W-0000 000
R/W-0
Table 72. CAL_DATA_EN Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R/W
0000 000
RESERVED
0
CAL_DATA_EN
R/W
0
Set this bit to enable the CAL_DATA register to enable reading
and writing of calibration data; see the calibration data register
for more information.


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