Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

ADC12DJ2700 Datasheet(PDF) 1 Page - Texas Instruments

Click here to check the latest version.
Part No. ADC12DJ2700
Description  5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
Download  146 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12DJ2700 Datasheet(HTML) 1 Page - Texas Instruments

  ADC12DJ2700 Datasheet HTML 1Page - Texas Instruments ADC12DJ2700 Datasheet HTML 2Page - Texas Instruments ADC12DJ2700 Datasheet HTML 3Page - Texas Instruments ADC12DJ2700 Datasheet HTML 4Page - Texas Instruments ADC12DJ2700 Datasheet HTML 5Page - Texas Instruments ADC12DJ2700 Datasheet HTML 6Page - Texas Instruments ADC12DJ2700 Datasheet HTML 7Page - Texas Instruments ADC12DJ2700 Datasheet HTML 8Page - Texas Instruments ADC12DJ2700 Datasheet HTML 9Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 1 / 146 page
background image
Input Frequency (GHz)
0
2
4
6
8
10
12
-15
-12
-9
-6
-3
0
3
D_BW
Single Channel Mode
Dual Channel Mode
Product
Folder
Order
Now
Technical
Documents
Tools &
Software
Support &
Community
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADC12DJ2700
SLVSEH9 – JANUARY 2018
ADC12DJ2700 5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel,
12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
1
1 Features
1
ADC Core:
12-Bit Resolution
Up to 5.4 GSPS in Single-Channel Mode
Up to 2.7 GSPS in Dual-Channel Mode
Performance Specifications:
Noise Floor (No Signal, VFS = 1.0 VPP-DIFF):
Dual-Channel Mode: –151.6 dBFS/Hz
Single-Channel Mode: –153.8 dBFS/Hz
HD2, HD3: –65 dBc up to 3 GHz
Buffered Analog Inputs With VCMI of 0 V:
Analog Input Bandwidth (–3 dB): 8.0 GHz
Usable Input Frequency Range: >10 GHz
Full-Scale Input Voltage (VFS, Default): 0.8 VPP
Analog Input Common-Mode (VICM): 0 V
Noiseless Aperture Delay (TAD) Adjustment:
Precise Sampling Control: 19-fs Step
Simplifies Synchronization and Interleaving
Temperature and Voltage Invariant delays
Easy-to-Use Synchronization Features
Automatic SYSREF Timing Calibration
Timestamp for Sample Marking
JESD204B Serial Data Interface:
Supports Subclass 0 and 1
Maximum Lane Rate: 12.8 Gbps
Up to 16 Lanes Allows Reduced Lane Rate
Digital Down-Converters in Dual-Channel Mode:
Real Output: DDC Bypass or 2x Decimation
Complex Output: 4x, 8x, or 16x Decimation
Four Independent 32-Bit NCOs per DDC
Power Consumption: 2.7 W
Power Supplies: 1.1 V, 1.9 V
ADC12DJ2700 Measured Input Bandwidth
2 Applications
Communications Testers (802.11ad, 5G)
Satellite Communications (SATCOM)
Phased Array Radar, SIGINT, and ELINT
Synthetic Aperture Radar (SAR)
Time-of-Flight and LIDAR Distance Measurement
Oscilloscopes and Wideband Digitizers
Microwave Backhaul
RF Sampling Software-Defined Radio (SDR)
Spectrometry
3 Description
The ADC12DJ2700 device is an RF-sampling, giga-
sample, analog-to-digital converter (ADC) that can
directly sample input frequencies from DC to above
10 GHz. In dual-channel mode, the ADC12DJ2700
can sample up to 2700 MSPS and up to 5400 MSPS
in single-channel mode. Programmable tradeoffs in
channel count (dual-channel mode) and Nyquist
bandwidth (single-channel mode) allow development
of flexible hardware that meets the needs of both high
channel
count
or
wide
instantaneous
signal
bandwidth applications. Full-power input bandwidth
(–3
dB)
of
8.0
GHz,
with
usable
frequencies
exceeding the –3-dB point in both dual- and single-
channel modes, allows direct RF sampling of L-band,
S-band, C-band, and X-band for frequency agile
systems.
The ADC12DJ2700 uses a high-speed JESD204B
output interface with up to 16 serialized lanes and
subclass-1 compliance for deterministic latency and
multi-device synchronization. The serial output lanes
support up to 12.8 Gbps and can be configured to
trade-off bit rate and number of lanes. Innovative
synchronization features, including noiseless aperture
delay (TAD) adjustment and SYSREF windowing,
simplify system design for phased array radar and
MIMO
communications.
Optional
digital
down
converters (DDCs) in dual-channel mode allow for
reduction
in
interface
rate
(real
and
complex
decimation modes) and digital mixing of the signal
(complex decimation modes only).
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
ADC12DJ2700
FCBGA (144) 10.00 mm × 10.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90  91  92  93  94  95  96  97  98  99  100   ...More


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn