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ADC12DJ2700 Datasheet(PDF) 86 Page - Texas Instruments

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Part No. ADC12DJ2700
Description  5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12DJ2700 Datasheet(HTML) 86 Page - Texas Instruments

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86
ADC12DJ2700
SLVSEH9 – JANUARY 2018
www.ti.com
Product Folder Links: ADC12DJ2700
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Copyright © 2018, Texas Instruments Incorporated
7.6.1.3 Miscellaneous Analog Registers (0x020 to 0x047)
Table 54. Miscellaneous Analog Registers
ADDRESS
RESET
ACRONYM
REGISTER NAME
SECTION
0x020-0x028
Undefined
RESERVED
RESERVED
0x029
0x00
CLK_CTRL0
Clock Control Register 0
Clock Control Register 0 (address = 0x029) [reset = 0x00]
0x02A
0x20
CLK_CTRL1
Clock Control Register 1
Clock Control Register 1 (address = 0x02A) [reset = 0x00]
0x02B
Undefined
RESERVED
RESERVED
0x02C-0x02E
Undefined
SYSREF_POS
SYSREF Capture Position Register
SYSREF Capture Position Register (address = 0x02C-
0x02E) [reset = Undefined]
0x02F
Undefined
RESERVED
RESERVED
0x030-0x031
0xA000
FS_RANGE_A
INA Full-Scale Range Adjust Register
INA Full-Scale Range Adjust Register (address = 0x030-
0x031) [reset = 0xA000]
0x032-0x033
0xA000
FS_RANGE_B
INB Full-Scale Range Adjust Register
INB Full-Scale Range Adjust Register (address = 0x032-
0x033) [reset = 0xA000]
0x034-0x037
Undefined
RESERVED
RESERVED
0x038
0x00
BG_BYPASS
Internal Reference Bypass Register
Internal Reference Bypass Register (address = 0x038)
[reset = 0x00]
0x039-0x03A
Undefined
RESERVED
RESERVED
0x03B
0x00
SYNC_CTRL
TMSTP± Control Register
TMSTP± Control Register (address = 0x03B) [reset =
0x00]
0x03C-0x047
Undefined
RESERVED
RESERVED
7.6.1.3.1
Clock Control Register 0 (address = 0x029) [reset = 0x00]
Figure 95. Clock Control Register 0 (CLK_CTRL0)
7
6
5
4
3
2
1
0
RESERVED
SYSREF_PROC_EN
SYSREF_RECV_EN
SYSREF_ZOOM
SYSREF_SEL
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0000
Table 55. CLK_CTRL0 Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R/W
0
RESERVED
6
SYSREF_PROC_EN
R/W
0
This bit enables the SYSREF processor. This bit must be set to
allow the device to process SYSREF events.
SYSREF_RECV_EN must be set before setting
SYSREF_PROC_EN.
5
SYSREF_RECV_EN
R/W
0
Set this bit to enable the SYSREF receiver circuit.
4
SYSREF_ZOOM
R/W
0
Set this bit to zoom in the SYSREF strobe status (affects
SYSREF_POS).
3-0
SYSREF_SEL
R/W
0000
Set this field to select which SYSREF delay to use. Set this field
based on the results returned by SYSREF_POS. Set this field to
0 to use SYSREF calibration.


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