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ADC12DJ2700 Datasheet(PDF) 80 Page - Texas Instruments

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Part No. ADC12DJ2700
Description  5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12DJ2700 Datasheet(HTML) 80 Page - Texas Instruments

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ADC12DJ2700
SLVSEH9 – JANUARY 2018
www.ti.com
Product Folder Links: ADC12DJ2700
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Register Maps (continued)
Memory Map (continued)
ADDRESS
RESET
ACRONYM
TYPE
REGISTER NAME
0x085
Undefined
TADJ_B_BG0
R/W
Timing Adjustment for B-ADC, Single-Channel Mode,
Background Calibration Register
0x086
Undefined
TADJ_A
R/W
Timing Adjustment for A-ADC, Dual-Channel Mode Register
0x087
Undefined
TADJ_CA
R/W
Timing Adjustment for C-ADC Acting for A-ADC, Dual-
Channel Mode Register
0x088
Undefined
TADJ_CB
R/W
Timing Adjustment for C-ADC Acting for B-ADC, Dual-
Channel Mode Register
0x089
Undefined
TADJ_B
R/W
Timing Adjustment for B-ADC, Dual-Channel Mode Register
0x08A-0x08B
Undefined
OADJ_A_INA
R/W
Offset Adjustment for A-ADC and INA Register
0x08C-0x08D
Undefined
OADJ_A_INB
R/W
Offset Adjustment for A-ADC and INB Register
0x08E-0x08F
Undefined
OADJ_C_INA
R/W
Offset Adjustment for C-ADC and INA Register
0x090-0x091
Undefined
OADJ_C_INB
R/W
Offset Adjustment for C-ADC and INB Register
0x092-0x093
Undefined
OADJ_B_INA
R/W
Offset Adjustment for B-ADC and INA Register
0x094-0x095
Undefined
OADJ_B_INB
R/W
Offset Adjustment for B-ADC and INB Register
0x096
Undefined
RESERVED
R
RESERVED
0x097
0x00
OSFILT0
R/W
Offset Filtering Control 0
0x098
0x33
OSFILT1
R/W
Offset Filtering Control 1
0x099-0x0FF
Undefined
RESERVED
R
RESERVED
ADC BANK REGISTERS (0x100 to 0x15F)
0x100-0x101
Undefined
RESERVED
R
RESERVED
0x102
Undefined
B0_TIME_0
R/W
Timing Adjustment for Bank 0 (0° Clock) Register
0x103
Undefined
B0_TIME_90
R/W
Timing Adjustment for Bank 0 (–90° Clock) Register
0x104-0x111
Undefined
RESERVED
R
RESERVED
0x112
Undefined
B1_TIME_0
R/W
Timing Adjustment for Bank 1 (0° Clock) Register
0x113
Undefined
B1_TIME_90
R/W
Timing Adjustment for Bank 1 (–90° Clock) Register
0x114-0x121
Undefined
RESERVED
R
RESERVED
0x122
Undefined
B2_TIME_0
R/W
Timing Adjustment for Bank 2 (0° Clock) Register
0x123
Undefined
B2_TIME_90
R/W
Timing Adjustment for Bank 2 (–90° Clock) Register
0x124-0x131
Undefined
RESERVED
R
RESERVED
0x132
Undefined
B3_TIME_0
R/W
Timing Adjustment for Bank 3 (0° Clock) Register
0x133
Undefined
B3_TIME_90
R/W
Timing Adjustment for Bank 3 (–90° Clock) Register
0x134-0x141
Undefined
RESERVED
R
RESERVED
0x142
Undefined
B4_TIME_0
R/W
Timing Adjustment for Bank 4 (0° Clock) Register
0x143
Undefined
B4_TIME_90
R/W
Timing Adjustment for Bank 4 (–90° Clock) Register
0x144-0x151
Undefined
RESERVED
R
RESERVED
0x152
Undefined
B5_TIME_0
R/W
Timing Adjustment for Bank 5 (0° Clock) Register
0x153
Undefined
B5_TIME_90
R/W
Timing Adjustment for Bank 5 (–90° Clock) Register
0x154-0x15F
Undefined
RESERVED
R
RESERVED
LSB CONTROL REGISTERS (0x160 to 0x1FF)
0x160
0x00
ENC_LSB
R/W
LSB Control Bit Output Register
0x161-0x1FF
Undefined
RESERVED
R
RESERVED
JESD204B REGISTERS (0x200 to 0x20F)
0x200
0x01
JESD_EN
R/W
JESD204B Enable Register
0x201
0x02
JMODE
R/W
JESD204B Mode (JMODE) Register
0x202
0x1F
KM1
R/W
JESD204B K Parameter Register
0x203
0x01
JSYNC_N
R/W
JESD204B Manual SYNC Request Register
0x204
0x02
JCTRL
R/W
JESD204B Control Register


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