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ADC12DJ2700 Datasheet(PDF) 78 Page - Texas Instruments

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Part No. ADC12DJ2700
Description  5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12DJ2700 Datasheet(HTML) 78 Page - Texas Instruments

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SCLK
1
24
Multiple Register Access
SCS
SDI
Command Field
Data Field (write mode)
SDO
(read mode)
Data Field
High Z
17
16
8
32
Data Field
High Z
25
Data Field (write mode)
A14
A13
A12
A1
1
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
78
ADC12DJ2700
SLVSEH9 – JANUARY 2018
www.ti.com
Product Folder Links: ADC12DJ2700
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Programming (continued)
7.5.1.5 Streaming Mode
The serial interface supports streaming reads and writes. In this mode, the initial 24 bits of the transaction
specifics the access type, register address, and data value as normal. Additional clock cycles of write or read
data are immediately transferred, as long as the SCS input is maintained in the asserted (logic low) state. The
register address auto increments (default) or decrements for each subsequent 8-bit transfer of the streaming
transaction. The ADDR_ASC bit (register 000h, bits 5 and 2) controls whether the address value ascends
(increments) or descends (decrements). Streaming mode can be disabled by setting the ADDR_HOLD bit (see
the user SPI configuration register). Figure 87 shows the streaming mode transaction details.
Figure 87. Serial Interface Protocol: Streaming Read/Write
See the Register Maps section for detailed information regarding the registers.
NOTE
The serial interface must not be accessed during ADC calibration. Accessing the serial
interface during this time impairs the performance of the device until the device is
calibrated correctly. Writing or reading the serial registers also reduces dynamic ADC
performance for the duration of the register access time.
7.6 Register Maps
The Memory Map lists all the ADC12DJ2700 registers.
Memory Map
ADDRESS
RESET
ACRONYM
TYPE
REGISTER NAME
STANDARD SPI-3.0 (0x000 to 0x00F)
0x000
0x30
CONFIG_A
R/W
Configuration A Register
0x001
Undefined
RESERVED
R
RESERVED
0x002
0x00
DEVICE_CONFIG
R/W
Device Configuration Register
0x003
0x03
CHIP_TYPE
R
Chip Type Register
0x004-0x005
0x0020
CHIP_ID
R
Chip ID Registers
0x006
0x0A
CHIP_VERSION
R
Chip Version Register
0x007-0x00B
Undefined
RESERVED
R
RESERVED
0x00C-0x00D
0x0451
VENDOR_ID
R
Vendor Identification Register
0x00E-0x00F
Undefined
RESERVED
R
RESERVED
USER SPI CONFIGURATION (0x010 to 0x01F)
0x010
0x00
USR0
R/W
User SPI Configuration Register
0x011-0x01F
Undefined
RESERVED
R
RESERVED


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