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ADC12DJ2700 Datasheet(PDF) 76 Page - Texas Instruments

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Part No. ADC12DJ2700
Description  5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12DJ2700 Datasheet(HTML) 76 Page - Texas Instruments

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76
ADC12DJ2700
SLVSEH9 – JANUARY 2018
www.ti.com
Product Folder Links: ADC12DJ2700
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
7.4.8 Trimming
Table 44 lists the parameters that can be trimmed and the associated registers.
Table 44. Trim Register Descriptions
TRIM PARAMETER
TRIM REGISTER
NOTES
Band-gap reference
BG_TRIM
Measurement on BG output pin.
Input termination resistance
RTRIM_x,
where x = A for INA± or B for INB±)
The device must be powered on with a clock
applied.
Input offset voltage
OADJ_x_VINy,
where x = ADC core (A, B or C)
and y = A for INA± or B for INB±)
A different trim value is allowed for each
ADC core (A, B, or C) to allow more
consistent offset performance in background
calibration mode.
INA± and INB± gain
GAIN_TRIM_x,
where x = A for INA± or B for INB±)
Set FS_RANGE_A and FS_RANGE_B to
default values before trimming the input. Use
FS_RANGE_A and FS_RANGE_B to adjust
the full-scale input voltage.
INA± and INB± full-scale input voltage
FS_RANGE_x,
where x = A for INA± or B for INB±)
Full-scale input voltage adjustment for each
input. The default value is effected by
GAIN_TRIM_x (x = A or B). Trim
GAIN_TRIM_x with FS_RANGE_x set to the
default value. FS_RANGE_x can then be
used to trim the full-scale input voltage.
Intra-ADC core timing (bank timing)
Bx_TIME_y,
where x = bank number (0–5)
and y = 0° or –90° clock phase
Trims the timing between the two banks of
an ADC core (ADC A, B, or C) for two clock
phases, either 0° or –90°. The –90° clock
phase is used in single-channel mode only.
Inter-ADC core timing (dual-channel mode)
TADJ_A, TADJ_B, TADJ_CA, TADJ_CB
The suffix letter (A, B, CA, or CB) indicates
the ADC core that is being trimmed. CA
indicates the timing trim in background
calibration mode for ADC C when standing in
for ADC A, whereas CB is the timing trim for
ADC C when standing in for ADC B.
Inter-ADC core timing (single-channel mode)
TADJ_A_FG90, TADJ_B_FG0,
TADJ_A_BG90, TADJ_C_BG0,
TADJ_C_BG90, TADJ_B_BG0
The middle letter (A, B, or C) indicates the
ADC core that is being trimmed. FG indicates
a trim for foreground calibration while BG
indicates background calibration. The suffix
of 0 or 90 indicates the clock phase applied
to the ADC core. 0 indicates a 0° clock and is
sampling in-phase with the clock input. 90
indicates a 90° clock and therefore is
sampling out-of-phase with the clock input.
These timings must be trimmed for optimal
performance if the user prefers to use INB±
in single-channel mode. These timings are
trimmed for INA± at the factory.
7.4.9 Offset Filtering
The ADC12DJ2700 has an additional feature that can be enabled to reduce offset-related interleaving spurs at fS
/ 2 and fS / 4 (single input mode only). Offset filtering is enabled via CAL_OSFILT. The OSFILT_BW and
OSFILT_SOAK parameters can be adjusted to tradeoff offset spur reduction with potential impact on information
in the mission mode signal being processed. Set these two parameters to the same value under most situations.
The DC_RESTORE setting is used to either retain or filter out all DC-related content in the signal.


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