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ADC12DJ2700 Datasheet(PDF) 75 Page - Texas Instruments

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Part No. ADC12DJ2700
Description  5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12DJ2700 Datasheet(HTML) 75 Page - Texas Instruments

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ADC12DJ2700
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SLVSEH9 – JANUARY 2018
Product Folder Links: ADC12DJ2700
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Copyright © 2018, Texas Instruments Incorporated
changes. Because of the additional active ADC core, background calibration mode has increased power
consumption in comparison to foreground calibration mode. The low-power background calibration (LPBG) mode
discussed in the Low-Power Background Calibration (LPBG) Mode section provides reduced average power
consumption in comparison with the standard background calibration mode. Background calibration can be
enabled by setting CAL_BG (see the calibration configuration 0 register). CAL_TRIG_EN must be set to 0 and
CAL_SOFT_TRIG must be set to 1.
Great care has been taken to minimize effects on converted data as the core switching process occurs, however,
small brief glitches may still occur on the converter data as the cores are swapped. See the Typical
Characteristics section for examples of possible glitches in sine-wave and DC signals.
7.4.6.3 Low-Power Background Calibration (LPBG) Mode
Low-power background calibration (LPBG) mode reduces the power-overhead of enabling additional ADC cores.
Off-line cores are powered down until ready to be calibrated and put on-line. Set LP_EN = 1 to enable the low-
power background calibration feature. LP_SLEEP_DLY is used to adjust the amount of time an ADC sleeps
before waking up for calibration (if LP_EN = 1 and LP_TRIG = 0). LP_WAKE_DLY sets how long the core is
allowed to stabilize before calibration and being put on-line. LP_TRIG is used to select between an automatic
switching process or one that is controlled by the user via CAL_SOFT_TRIG or CAL_TRIG. In this mode there is
an increase in power consumption during the ADC core calibration. The power consumption roughly alternates
between the power consumption in foreground calibration when the spare ADC core is sleeping to the power
consumption in background calibration when the spare ADC is being calibrated. Design the power-supply
network to handle the transient power requirements for this mode.
7.4.7 Offset Calibration
Foreground calibration and background calibration modes inherently calibrate the offsets of the ADC cores;
however, the input buffers sit outside of the calibration loop and therefore their offsets are not calibrated by the
standard calibration process. In both dual-channel mode and single-channel mode, uncalibrated input buffer
offsets result in a shift in the mid-code output (DC offset) with no input. Further, in single-channel mode
uncalibrated input buffer offsets can result in a fixed spur at fS / 2. A separate calibration is provided to correct
the input buffer offsets.
There must be no signals at or near DC or aliased signals that fall at or near DC in order to properly calibration
the offsets, requiring the system to ensure this condition during normal operation or have the ability to mute the
input signal during calibration. Foreground offset calibration is enabled via CAL_OS and only performs the
calibration one time as part of the foreground calibration procedure. Background offset calibration is enabled via
CAL_BGOS and continues to correct the offset as part of the background calibration routine to account for
operating condition changes. When CAL_BGOS is set, the system must ensure that there are no DC or near DC
signals or aliased signals that fall at or near DC during normal operation. Offset calibration can be performed as
a foreground operation when using background calibration by setting CAL_OS to 1 before setting CAL_EN, but
does not correct for variations as operating conditions change.
The offset calibration correction uses the input offset voltage trim registers (see Table 44) to correct the offset
and therefore must not be written by the user when offset calibration is used. The user can read the calibrated
values by reading the OADJ_x_VINy registers, where x is the ADC core and y is the input (INA± or INB±), after
calibration is completed. Only read the values when FG_DONE is read as 1 when using foreground offset
calibration (CAL_OS = 1) and do not read the values when using background offset calibration (CAL_BGOS = 1).


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