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ADC12DJ2700 Datasheet(PDF) 73 Page - Texas Instruments

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Part No. ADC12DJ2700
Description  5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12DJ2700 Datasheet(HTML) 73 Page - Texas Instruments

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ADC12DJ2700
www.ti.com
SLVSEH9 – JANUARY 2018
Product Folder Links: ADC12DJ2700
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Copyright © 2018, Texas Instruments Incorporated
7.4.5.8 Modified RPAT Test Mode
A 12-octet repeating pattern is defined in INCITS TR-35-2004. The purpose of this pattern is to generate white
spectral content for JESD204B compliance and jitter testing. Table 43 lists the pattern before and after 8b, 10b
encoding.
Table 43. Modified RPAT Pattern Values
OCTET NUMBER
Dx.y NOTATION
8-BIT INPUT TO 8b, 10b ENCODER
20b OUTPUT OF 8b, 10b ENCODER
(Two Characters)
0
D30.5
0xBE
0x86BA6
1
D23.6
0xD7
2
D3.1
0x23
0xC6475
3
D7.2
0x47
4
D11.3
0x6B
0xD0E8D
5
D15.4
0x8F
6
D19.5
0xB3
0xCA8B4
7
D20.0
0x14
8
D30.2
0x5E
0x7949E
9
D27.7
0xFB
10
D21.1
0x35
0xAA665
11
D25.2
0x59
7.4.6 Calibration Modes and Trimming
The ADC12DJ2700 has two calibration modes available: foreground calibration and background calibration.
When foreground calibration is initiated the ADCs are automatically taken offline and the output data becomes
mid-code (0x000 in 2's complement) while a calibration is occurring. Background calibration allows the ADC to
continue normal operation while the ADC cores are calibrated in the background by swapping in a different ADC
core to take its place. Additional offset calibration features are available in both foreground and background
calibration modes. Further, a number of ADC parameters can be trimmed to optimize performance in a user
system.
The ADC12DJ2700 consists of a total of six sub-ADCs, each referred to as a bank, with two banks forming an
ADC core. The banks sample out-of-phase so that each ADC core is two-way interleaved. The six banks form
three ADC cores, referred to as ADC A, ADC B, and ADC C. In foreground calibration mode, ADC A samples
INA± and ADC B samples INB± in dual-channel mode and both ADC A and ADC B sample INA± (or INB±) in
single-channel mode. In the background calibration modes, the third ADC core, ADC C, is swapped in
periodically for ADC A and ADC B so that they can be calibrated without disrupting operation. Figure 85
illustrates a diagram of the calibration system including labeling of the banks that make up each ADC core. When
calibration is performed the linearity, gain, and offset voltage for each bank are calibrated to an internally
generated calibration signal. The analog inputs can be driven during calibration, both foreground and
background, except that when offset calibration (OS_CAL or BGOS_CAL) is used there must be no signals (or
aliased signals) near DC for proper estimation of the offset (see the Offset Calibration section).


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