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ADC12DJ2700 Datasheet(PDF) 72 Page - Texas Instruments

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Part No. ADC12DJ2700
Description  5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12DJ2700 Datasheet(HTML) 72 Page - Texas Instruments

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ADC12DJ2700
SLVSEH9 – JANUARY 2018
www.ti.com
Product Folder Links: ADC12DJ2700
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Copyright © 2018, Texas Instruments Incorporated
7.4.5.4.2
Long Transport Test Pattern
The long-transport test mode is used in all of the JMODE modes where N' equals 16. Patterns are generated in
accordance with the JESD204B standard and are different for each output format as defined in Table 19. The
rules for the pattern are defined below. Equation 11 gives the length of the test pattern. The long transport test
pattern is the same for link A and link B, where DAx lanes belong to link A and DBx lanes belong to link B.
Long Test Pattern Length (Frames) = K × ceil[(M × S + 2) / K]
(11)
Sample Data:
Frame 0: Each sample contains N bits, with all samples set to the converter ID (CID) plus 1 (CID + 1). The
CID is defined based on the converter number within the link; two links are used in all modes except
JMODE 15. Within a link, the converters are numbered by channel (A or B) and in-phase (I) and
quadrature-phase (Q) and reset between links. For instance, in JMODE 10, two links are used so channel
A and B data are separated into separate links and the in-phase component for each channel has CID = 0
and the quadrature-phase component has CID = 1. In JMODE 15, one link is used, so channel A and B
are within the same link and AI has CID = 0, AQ has CID = 1, BI has CID = 2, and BQ has CID = 3.
Frame 1: Each sample contains N bits, with each sample (for each converter) set as its individual sample
ID (SID) within the frame plus 1 (SID + 1)
Frame 2 +: Each sample contains N bits, with the data set to 2N–1 for all samples (for example, if N is 15
then 2N–1 = 16384)
Control Bits (if CS > 0):
Frame 0 to M × S – 1: The control bit belonging to the sample mod (i, S) of the converter floor (i, S) is set
to 1 and all others are set to 0, where i is the frame index (i = 0 is the first frame of the pattern).
Essentially, the control bit walks from the lowest indexed sample to the highest indexed sample and from
the lowest indexed converter to the highest indexed converter, changing position every frame.
Frame M × S +: All control bits are set to 0
Table 42 describes an example long transport test pattern for when JMODE = 10, K = 10.
Table 42. Example Long Transport Test Pattern (JMODE = 10, K = 10)
TIME
PATTERN REPEATS
OCTET
NUM
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
DA0
0x0003
0x0002
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x0003
DA1
0x0004
0x0003
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x0004
DB0
0x0003
0x0002
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x0003
DB1
0x0004
0x0003
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x0004
Frame
n
Frame
n + 1
Frame
n + 2
Frame
n + 3
Frame
n + 4
Frame
n + 5
Frame
n + 6
Frame
n + 7
Frame
n + 8
Frame
n + 9
Frame
n + 10
The pattern starts at the end of the initial lane alignment sequence (ILAS) and repeats indefinitely as long as the
link remains running. For more details see the JESD204B specification, section 5.1.6.3.
7.4.5.5 D21.5 Test Mode
In this test mode, the controller transmits a continuous stream of D21.5 characters (alternating 0s and 1s).
7.4.5.6 K28.5 Test Mode
In this test mode, the controller transmits a continuous stream of K28.5 characters.
7.4.5.7 Repeated ILA Test Mode
In this test mode, the JESD204B link layer operates normally, except that the ILA sequence (ILAS) repeats
indefinitely instead of starting the data phase. Whenever the receiver issues a synchronization request, the
transmitter initiates code group synchronization. Upon completion of code group synchronization, the transmitter
repeatedly transmits the ILA sequence.


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