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ADC12DJ2700 Datasheet(PDF) 69 Page - Texas Instruments

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Part No. ADC12DJ2700
Description  5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12DJ2700 Datasheet(HTML) 69 Page - Texas Instruments

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DIG_BIND_A = 0
ADC
Channel A
ADC
Channel B
JESD204B
LINK A
(DA0-DA7)
DDC A
JMODE
DDC Bypass
JESD204B
LINK B
(DB0-DB7)
DDC B
JMODE
DDC Bypass
DIG_BIND_B = 0
.
Copyright © 2017, Texas Instruments Incorporated
69
ADC12DJ2700
www.ti.com
SLVSEH9 – JANUARY 2018
Product Folder Links: ADC12DJ2700
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Figure 83. Dual DDC Mode or Redundant Data Mode for Channel A
7.4.4 Power-Down Modes
The PD input pin allows the ADC12DJ2700 devices to be entirely powered down. Power-down can also be
controlled by MODE (see the device configuration register). The serial data output drivers are disabled when PD
is high. When the device returns to normal operation, the JESD204 link must be re-established, and the ADC
pipeline and decimation filters contain meaningless information so the system must wait a sufficient time for the
data to be flushed. If power-down for power savings is desired, the system must power down the supply voltages
regulators for VA19, VA11, and VD11 rather than make use of the PD input or MODE settings.
NOTE
Powering down high speed data outputs (DA0± ... DA7±, DB0± ... DB7±) for extended
times may reduce performance of the output serializers, especially at high data rates. For
information regarding reliable serializer operation, see footnote 1 in the Pin Functions
table.
7.4.5 Test Modes
A number of device test modes are available. These modes insert known patterns of information into the device
data path for assistance with system debug, development, or characterization.
7.4.5.1 Serializer Test-Mode Details
Test modes are enabled by setting JTEST (see the JESD204B test pattern control register) to the desired test
mode. Each test mode is described in detail in the following sections. Regardless of the test mode, the serializer
outputs are powered up based on JMODE. Only enable the test modes when the JESD204B link is disabled.
Figure 84 provides a diagram showing the various test mode insertion points.


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