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ADC12DJ2700 Datasheet(PDF) 61 Page - Texas Instruments

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Part No. ADC12DJ2700
Description  5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12DJ2700 Datasheet(HTML) 61 Page - Texas Instruments

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ADC12DJ2700
www.ti.com
SLVSEH9 – JANUARY 2018
Product Folder Links: ADC12DJ2700
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Copyright © 2018, Texas Instruments Incorporated
There are a number of parameters required to define the JESD204B format, all of which are sent across the link
during the initial lane alignment sequence. In the ADC12DJ2700, most parameters are automatically derived
based on the selected JMODE; however, a few are configured by the user. Table 18 describes these
parameters.
Table 18. JESD204B Initial Lane Alignment Sequence Parameters
PARAMETER
DESCRIPTION
USER CONFIGURED
OR DERIVED
VALUE
ADJCNT
LMFC adjustment amount (not applicable)
Derived
Always 0
ADJDIR
LMFC adjustment direction (not applicable)
Derived
Always 0
BID
Bank ID
Derived
Always 0
CF
Number of control words per frame
Derived
Always 0
CS
Control bits per sample
Derived
Always set to 0 in ILAS, see Table 19 for
actual usage
DID
Device identifier, used to identify the link
User configured
Set by DID (see the JESD204B DID
parameter register), see Table 20
F
Number of octets (bytes) per frame (per
lane)
Derived
See Table 19
HD
High-density format (samples split between
lanes)
Derived
Always 0
JESDV
JESD204 standard revision
Derived
Always 1
K
Number of frames per multiframe
User configured
Set by the KM1 register, see the JESD204B
K parameter register
L
Number of serial output lanes per link
Derived
See Table 19
LID
Lane identifier for each lane
Derived
See Table 20
M
Number of converters used to determine
lane bit packing; may not match number of
ADC channels in the device
Derived
See Table 19
N
Sample resolution (before adding control
and tail bits)
Derived
See Table 19
N'
Bits per sample after adding control and tail
bits
Derived
See Table 19
S
Number of samples per converter (M) per
frame
Derived
See Table 19
SCR
Scrambler enabled
User configured
Set by the JESD204B control register
SUBCLASSV
Device subclass version
Derived
Always 1
RES1
Reserved field 1
Derived
Always 0
RES2
Reserved field 2
Derived
Always 0
CHKSUM
Checksum for ILAS checking (sum of all
above parameters modulo 256)
Derived
Computed based on parameters in this table
Configuring the ADC12DJ2700 is made easy by using a single configuration parameter called JMODE (see the
JESD204B mode register). Using Table 19, the correct JMODE value can be found for the desired operating
mode. The modes listed in Table 19 are the only available operating modes. This table also gives a range and
allowable step size for the K parameter (set by KM1, see the JESD204B K parameter register), which sets the
multiframe length in number of frames.


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