Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

ADC12DJ2700 Datasheet(PDF) 60 Page - Texas Instruments

Click here to check the latest version.
Part No. ADC12DJ2700
Description  5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
Download  146 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12DJ2700 Datasheet(HTML) 60 Page - Texas Instruments

Back Button ADC12DJ2700 Datasheet HTML 56Page - Texas Instruments ADC12DJ2700 Datasheet HTML 57Page - Texas Instruments ADC12DJ2700 Datasheet HTML 58Page - Texas Instruments ADC12DJ2700 Datasheet HTML 59Page - Texas Instruments ADC12DJ2700 Datasheet HTML 60Page - Texas Instruments ADC12DJ2700 Datasheet HTML 61Page - Texas Instruments ADC12DJ2700 Datasheet HTML 62Page - Texas Instruments ADC12DJ2700 Datasheet HTML 63Page - Texas Instruments ADC12DJ2700 Datasheet HTML 64Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 60 / 146 page
background image
60
ADC12DJ2700
SLVSEH9 – JANUARY 2018
www.ti.com
Product Folder Links: ADC12DJ2700
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
7.4 Device Functional Modes
The ADC12DJ2700 can be configured to operate in a number of functional modes. These modes are described
in this section.
7.4.1 Dual-Channel Mode
The ADC12DJ2700 can be used as a dual-channel ADC where the sampling rate is equal to the clock frequency
(fS = fCLK) provided at the CLK+ and CLK– pins. The two inputs, AIN± and BIN±, serve as the respective inputs
for each channel in this mode. This mode is chosen simply by setting JMODE to the appropriate setting for the
desired configuration as described in Table 19. The analog inputs can be swapped by setting DUAL_INPUT (see
the input mux control register)
7.4.2 Single-Channel Mode (DES Mode)
The ADC12DJ2700 can also be used as a single-channel ADC where the sampling rate is equal to two times the
clock frequency (fS = 2 × fCLK) provided at the CLK+ and CLK– pins. This mode effectively interleaves the two
ADC channels together to form a single-channel ADC at twice the sampling rate. This mode is chosen simply by
setting JMODE to the appropriate setting for the desired configuration as described in Table 19. Either analog
input, INA± or INB±, can serve as the input to the ADC, however INA± is recommended for best performance.
The analog input can be selected using SINGLE_INPUT (see the input mux control register). The digital down-
converters cannot be used in single-channel mode.
NOTE
INA± is strongly recommended to be used as the input to the ADC for optimized
performance in single-channel mode.
7.4.3 JESD204B Modes
The ADC12DJ2700 can be programmed as a single-channel or dual-channel ADC, with or without decimation,
and a number JESD204B output formats. Table 17 summarizes the basic operating mode configuration
parameters and whether they are user configured or derived.
NOTE
Powering down high-speed data outputs (DA0± ... DA7±, DB0± ... DB7±) for extended
times can reduce performance of the output serializers, especially at high data rates. For
information regarding reliable serializer operation, see footnote 1 in the Pin Functions
table.
Table 17. ADC12DJ2700 Operating Mode Configuration Parameters
PARAMETER
DESCRIPTION
USER CONFIGURED
OR DERIVED
VALUE
JMODE
JESD204B operating mode, automatically
derives the rest of the JESD204B
parameters, single-channel or dual-channel
mode and the decimation factor
User configured
Set by JMODE (see the JESD204B mode
register)
D
Decimation factor
Derived
See Table 19
DES
1 = single-channel mode, 0 = dual-channel
mode
Derived
See Table 19
R
Number of bits transmitted per lane per
DEVCLK cycle. The JESD204B line rate is
the DEVCLK frequency times R. This
parameter sets the SerDes PLL
multiplication factor or controls bypassing of
the SerDes PLL.
Derived
See Table 19
Links
Number of JESD204B links used
Derived
See Table 19
K
Number of frames per multiframe
User configured
Set by KM1 (see the JESD204B K
parameter register), see the allowed values
in Table 19


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90  91  92  93  94  95  96  97  98  99  100   ...More


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn