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ADC12DJ2700 Datasheet(PDF) 58 Page - Texas Instruments

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Part No. ADC12DJ2700
Description  5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12DJ2700 Datasheet(HTML) 58 Page - Texas Instruments

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TX LMFC
RX LMFC
ADC 1 Data
Propagation
tTX
tPCB
tRX-DESER
Time
ADC 2 Data
Propagation
tTX
tPCB
Invalid Region
of LMFC
Valid Region
of LMFC
Nominal Link Delay
(Arrival at Elastic Buffer)
Link Delay
Variation
Choose LMFC
edge as release
point (RBD = 0)
Release point
margin
tRX-DESER
58
ADC12DJ2700
SLVSEH9 – JANUARY 2018
www.ti.com
Product Folder Links: ADC12DJ2700
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Copyright © 2018, Texas Instruments Incorporated
Figure 82. LMFC Valid Region Definition for Elastic Buffer Release Point Selection
The TX and RX LMFCs do not necessarily need to be phase aligned, but knowledge of their phase is important
for proper elastic buffer release point selection. Also, the elastic buffer release point occurs within every LMFC
cycle, but the buffers only release when all lanes have arrived. Therefore, the total link delay can exceed a single
LMFC period; see JESD204B multi-device synchronization: Breaking down the requirements for more
information.
7.3.7.7 Operation in Subclass 0 Systems
The ADC12DJ2700 can operate with subclass 0 compatibility provided that multi-ADC synchronization and
deterministic latency are not required. With these limitations, the device can operate without the application of
SYSREF. The internal local multiframe clock is automatically self-generated with unknown timing. SYNC is used
as normal to initiate the CGS and ILA.
7.3.8 Alarm Monitoring
A number of built-in alarms are available to monitor internal events. Several types of alarms and upsets are
detected by this feature:
1. Serializer PLL is not locked
2. JESD204B link is not transmitting data (not in the data transmission state)
3. SYSREF causes internal clocks to be realigned
4. An upset that impacts the NCO
5. An upset that impacts the internal clocks
When an alarm occurs, a bit for each specific alarm is set in ALM_STATUS. Each alarm bit remains set until the
host system writes a 1 to clear the alarm. If the alarm type is not masked (see the alarm mask register), then the
alarm is also indicated by the ALARM register. The CALSTAT output pin can be configured as an alarm output
that goes high when an alarm occurs; see the CAL_STATUS_SEL bit in the calibration pin configuration register.
7.3.8.1 NCO Upset Detection
The NCO_ALM register bit indicates if the NCO in channel A or B has been upset. The NCO phase accumulators
in channel A are continuously compared to channel B. If the accumulators differ for even one clock cycle, the
NCO_ALM register bit is set and remains set until cleared by the host system by writing a 1. This feature
requires the phase and frequency words for each NCO accumulator in DDC A (PHASEAx, FREQAx) to be set to
the same values as the NCO accumulators in DDC B (PHASEBx, FREQBx). For example, PHASEA0 must be
the same as PHASEB0 and FREQA0 must be the same as FREQB0, however, PHASEA1 can be set to a
different value than PHASEA0. This requirement ultimately reduces the number of NCO frequencies available for
phase coherent frequency hopping from four to two for each DDC. DDC B can use a different NCO frequency
than DDC A by setting the NCOB[1:0] pins to a different value than NCOA[1:0]. This detection is only valid after
the NCOs are synchronized by either SYSREF or the start of the ILA sequence (as determined by the NCO
synchronization register). For the NCO upset detection to work properly, follow these steps:


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