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ADC12DJ2700 Datasheet(HTML) 56 Page - Texas Instruments
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SLVSEH9 – JANUARY 2018
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Copyright © 2018, Texas Instruments Incorporated
An optional data scrambler can be used to scramble the octets before transmission across the channel.
Scrambling is recommended in order to remove the possibility of spectral peaks in the transmitted data. The
JESD204B receiver automatically synchronizes its descrambler to the incoming scrambled data stream. The
initial lane alignment sequence (ILA) is never scrambled. Scrambling can be enabled by setting SCR (in the
JESD204B control register).
184.108.40.206 Link Layer
The link layer serves multiple purposes in JESD204B, including establishing the code boundaries (see the Code
Group Synchronization (CGS) section), initializing the link (see the Initial Lane Alignment Sequence (ILAS)
section), encoding the data (see the 8b, 10b Encoding section), and monitoring the health of the link (see the
Frame and Multiframe Monitoring section).
Code Group Synchronization (CGS)
The first step in initializing the JESD204B link, after SYSREF is processed, is to achieve code group
synchronization. The receiver first asserts the SYNC signal when ready to initialize the link. The transmitter
responds to the request by sending a stream of K28.5 characters. The receiver then aligns its character clock to
the K28.5 character sequence. Code group synchronization is achieved after receiving four K28.5 characters
successfully. The receiver deasserts SYNC on the next local multiframe clock (LMFC) edge after CGS is
achieved and waits for the transmitter to start the initial lane alignment sequence.
Initial Lane Alignment Sequence (ILAS)
After the transmitter detects the SYNC signal deassert, the transmitter waits until its next LMFC edge to start
sending the initial lane alignment sequence. The ILAS consists of four multiframes each containing a
predetermined sequence. The receiver searches for the start of the ILAS to determine the frame and multiframe
boundaries. As the ILAS reaches the receiver for each lane, the lane starts to buffer its data until all receivers
have received the ILAS and subsequently release the ILAS from all lanes at the same time in order to align the
lanes. The second multiframe of the ILAS contains configuration parameters for the JESD204B that can be used
by the receiver to verify that the transmitter and receiver configurations match.
8b, 10b Encoding
The data link layer converts the 8-bit octets from the transport layer into 10-bit characters for transmission across
the link using 8b, 10b encoding. 8b, 10b encoding provides DC balance for AC-coupling of the SerDes links and
a sufficient number of edge transitions for the receiver to reliably recover the data clock. 8b, 10b also provides
some amount of error detection where a single bit error in a character likely results in either not being able to find
the 10-bit character in the 8b, 10b decoder lookup table or incorrect character disparity.
Frame and Multiframe Monitoring
The ADC12DJ2700 supports frame and multiframe monitoring for verifying the health of the JESD204B link. If
the last octet of a frame matches the last octet of the previous frame, then the last octet in the second frame is
replaced with an /F/ (/K28.7/) character. If the second frame is the last frame of a multiframe, then an /A/
(/K28.3/) character is used instead. When scrambling is enabled, if the last octet of a frame is 0xFC then the
transmitter replaces the octet with an /F/ (/K28.7/) character. With scrambling, if the last octet of a multiframe is
0x7C then the transmitter replaces the octet with an /A/ (/K28.3/) character. When the receiver detects an /F/ or
/A/ character, the receiver checks if the character occurs at the end of a frame or multiframe, and replaces that
octet with the appropriate data character. The receiver can report an error if the alignment characters occur in
the incorrect place and trigger a link realignment.
220.127.116.11 Physical Layer
The JESD204B physical layer consists of a current mode logic (CML) output driver and receiver. The receiver
consists of a clock detection and recovery (CDR) unit to extract the data clock from the serialized data stream
and can contain an equalizer to correct for the low-pass response of the physical transmission channel. Likewise,
the transmitter can contain pre-equalization to account for frequency dependent losses across the channel. The
total reach of the SerDes links depends on the data rate, board material, connectors, equalization, noise and
jitter, and required bit-error performance. The SerDes lanes do not have to be matched in length because the
receiver aligns the lanes during the initial lane alignment sequence.
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