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ADC12DJ2700 Datasheet(PDF) 55 Page - Texas Instruments

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Part No. ADC12DJ2700
Description  5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12DJ2700 Datasheet(HTML) 55 Page - Texas Instruments

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ADC
JESD204B
TRANSPORT
LAYER
SCRAMBLER
(Optional)
JESD204B
LINK LAYER
JESD204B
TX
8b/10b
ENCODER
APPLICATION
LAYER
JESD204B
TRANSPORT
LAYER
DESCRAMBLE
(Optional)
JESD204B
LINK LAYER
JESD204B
RX
8b/10b
DECODER
ADC
JESD204B Block
Logic Device
JESD204B Block
ANALOG
CHANNEL
Copyright © 2017, Texas Instruments Incorporated
55
ADC12DJ2700
www.ti.com
SLVSEH9 – JANUARY 2018
Product Folder Links: ADC12DJ2700
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Copyright © 2018, Texas Instruments Incorporated
7.3.7 JESD204B Interface
The ADC12DJ2700 uses the JESD204B high-speed serial interface for data converters to transfer data from the
ADC to the receiving logic device. The ADC12DJ2700 serialized lanes are capable of operating up to 12.8 Gbps,
slightly above the JESD204B maximum lane rate. A maximum of 16 lanes can be used to allow lower lane rates
for interfacing with speed-limited logic devices. Figure 81 shows a simplified block diagram of the JESD204B
interface protocol.
Figure 81. Simplified JESD204B Interface Diagram
The various signals used in the JESD204B interface and the associated ADC12DJ2700 pin names are
summarized briefly in Table 16 for reference.
Table 16. Summary of JESD204B Signals
SIGNAL NAME
ADC12DJ2700 PIN NAMES
DESCRIPTION
Data
DA0+...DA7+, DA0–...DA7–, DB0+...DB7+, DB0–...DB7–
High-speed serialized data after 8b,
10b encoding
SYNC
SYNCSE, TMSTP+, TMSTP–
Link initialization signal (handshake),
toggles low to start code group
synchronization (CGS) process
Device clock
CLK+, CLK–
ADC sampling clock, also used for
clocking digital logic and output
serializers
SYSREF
SYSREF+, SYSREF–
System timing reference used to
deterministically reset the internal local
multiframe counters in each
JESD204B device
7.3.7.1 Transport Layer
The transport layer takes samples from the ADC output (in decimation bypass mode) or from the DDC output
and maps the samples into octets, frames, multiframes, and lanes. Sample mapping is defined by the JESD204B
mode that is used, defined by parameters such as L, M, F, S, N, N', CF, and so forth. There are a number of
predefined transport layer modes in the ADC12DJ2700 that are defined in Table 19. The high level configuration
parameters for the transport layer in the ADC12DJ2700 are described in Table 17. For simplicity, the transport
layer mode is chosen by simply setting the JMODE parameter and the desired K value. For reference, the
various configuration parameters for JESD204B are defined in Table 18.


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