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ADC12DJ2700 Datasheet(PDF) 53 Page - Texas Instruments

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Part No. ADC12DJ2700
Description  5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12DJ2700 Datasheet(HTML) 53 Page - Texas Instruments

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ADC12DJ2700
www.ti.com
SLVSEH9 – JANUARY 2018
Product Folder Links: ADC12DJ2700
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Copyright © 2018, Texas Instruments Incorporated
For maximum efficiency, a group of high-speed filter blocks are implemented with specific blocks used for each
decimation setting to achieve the composite responses illustrated in Figure 69 to Figure 80. Table 12 describes
the combination of filter blocks used for each decimation setting and Table 13 lists the coefficient details and
decimation factor of each filter block. The coefficients are symmetric with the center tap indicated by bold text.
Table 12. Decimation Mode Filter Usage
DECIMATION SETTING
FILTER BLOCKS USED
2
CS80
4 (D4_AP87 = 0)
CS45, CS80
4 (D4_AP87 = 1)
CS45, CS87
8
CS20, CS40, CS80
16
CS10, CS20, CS40, CS80
Table 13. Filter Coefficient Details
FILTER COEFFICIENT SET (Decimation Factor of Filter)
CS10 (2)
CS20 (2)
CS40 (2)
CS45 (2)
CS80 (2)
CS87 (2)
–65
–65
109
109
–327
–327
56
56
–37
–37
–15
–15
0
0
0
0
0
0
0
0
0
0
0
0
577
577
–837
–837
2231
2231
–401
–401
118
118
23
23
1024
0
0
0
0
0
0
0
0
0
0
4824
4824
–8881
–8881
1596
1596
–291
–291
–40
–40
8192
0
0
0
0
0
0
0
0
39742
39742
–4979
–4979
612
612
64
64
65536
0
0
0
0
0
0
20113
20113
–1159
–1159
–97
–97
32768
0
0
0
0
2031
2031
142
142
0
0
0
0
–3356
–3356
–201
–201
0
0
0
0
5308
5308
279
279
0
0
0
0
–8140
–8140
–380
–380
0
0
0
0
12284
12284
513
513
0
0
0
0
–18628
–18628
–690
–690
0
0
0
0
29455
29455
939
939
0
0
0
0
–53191
–53191
–1313
–1313
0
0
0
0
166059
166059
1956
1956
262144
0
0
–3398
–3398
0
0
10404
10404
16384
7.3.6.3 Output Data Format
The DDC output data varies depending on the selected JMODE. Real decimate-by-2 mode (JMODE 9) consists
of 15-bit real output data. Complex decimation modes (JMODE 10 to 16), except for JMODE 12, consist of 15-bit
complex data plus the two overrange threshold-detection control bits. JMODE 12 output data consists of 12-bit
complex data, but does not include the two overrange threshold-detection control bits that must instead be
monitored using the ORA0, ORA1 and ORB0, ORB1 output pins. Table 14 lists the data format for JMODE 9 and
Table 15 lists the data format for all JMODEs except JMODE 12.


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