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ADC12DJ2700 Datasheet(PDF) 50 Page - Texas Instruments

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Part No. ADC12DJ2700
Description  5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12DJ2700 Datasheet(HTML) 50 Page - Texas Instruments

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ADC12DJ2700
SLVSEH9 – JANUARY 2018
www.ti.com
Product Folder Links: ADC12DJ2700
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Copyright © 2018, Texas Instruments Incorporated
NCO synchronization using SYSREF (AC-coupled):
1. The device must be programmed for normal operation
2. Set JESD_EN to 1 to start the JESD204B link (the SYNC signal can respond as normal during the CGS
process)
3. Program FREQAx, FREQBx, PHASEAx, and PHASEBx to the desired settings
4. Run SYSREF continuously
5. Arm NCO synchronization by setting NCO_SYNC_NEXT to 1 at the same time at all ADCs by timing the
rising edge of SCLK for the last data bit (LSB) at the end of the SPI write so that the SCLK rising edge
occurs after a SYSREF rising edge and early enough before the next SYSREF rising edge so that the trigger
is armed before the next SYSREF rising edge (a long SYSREF period is recommended)
6. NCOs in all ADCs are synchronized by the next SYSREF rising edge
7.3.6.2 Decimation Filters
The decimation filters are arranged to provide a programmable overall decimation of 2, 4, 8, or 16. All filter
outputs have a resolution of 15 bits. The decimate-by-2 filter has a real output and the decimate-by-4, decimate-
by-8, and decimate-by-16 filters have complex outputs. Table 11 lists the effective output sample rates, available
signal bandwidths, output formats, and stop-band attenuation for each decimation mode. The available
bandwidths of the complex output modes are twice that of equivalent real decimation modes because of the
nature of the I/Q data and complex signaling. This higher bandwidth results in the decimate-by-2 real and
decimate-by-4 complex modes having approximately the same useful output bandwidth.
Table 11. Output Sample Rates and Signal Bandwidths
DECIMATION
SETTING
ƒ(DEVCLK)
OUTPUT FORMAT
OUTPUT RATE
(MSPS)
MAX ALIAS PROTECTED SIGNAL
BANDWIDTH (MHz)
STOP-BAND
ATTENUATION
PASS-BAND
RIPPLE
No decimation
ƒ(DEVCLK)
ƒ(DEVCLK) / 2
< ±0.001 dB
Real signal,
12-bit data
Decimate-by-2
ƒ(DEVCLK) / 2
0.4 × ƒ(DEVCLK) / 2
> 89 dB
< ±0.001 dB
Real signal,
15-bit data
Decimate-by-4
(D4_AP87 = 0)
ƒ(DEVCLK) / 4
0.8 × ƒ(DEVCLK) / 4
> 90 dB
< ±0.001 dB
Complex signal,
15-bit data
Decimate-by-4
(D4_AP87 = 1)
ƒ(DEVCLK) / 4
0.875 × ƒ(DEVCLK) / 4
> 66 dB
< ±0.005 dB
Complex signal,
15-bit data
Decimate-by-8
ƒ(DEVCLK) / 8
0.8 × ƒ(DEVCLK) / 8
> 90 dB
< ±0.001 dB
Complex signal,
15-bit data
Decimate-by-16
ƒ(DEVCLK) / 16
0.8 × ƒ(DEVCLK) / 16
> 90 dB
< ±0.001 dB
Complex signal,
15-bit data
Figure 69 to Figure 80 provide the composite decimation filter responses. The pass-band section (black trace)
shows the alias-protected region of the response. The transition band (red trace) shows the transition region of
the response, or the regions that alias into the transition region, which is not alias protected and therefore
desired signals must not be within this band. The aliasing band (blue trace) shows the attenuation applied to the
bands that alias back into the pass band after decimation and are sufficiently low to prevent undesired signals
from showing up in the pass band. Use analog input filtering for additional attenuation of the aliasing band or to
prevent harmonics, interleaving spurs, or other undesired spurious signals from folding into the desired signal
band before the decimation filter.


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