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ADC12DJ2700 Datasheet(PDF) 49 Page - Texas Instruments

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Part No. ADC12DJ2700
Description  5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12DJ2700 Datasheet(HTML) 49 Page - Texas Instruments

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ADC12DJ2700
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SLVSEH9 – JANUARY 2018
Product Folder Links: ADC12DJ2700
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Copyright © 2018, Texas Instruments Incorporated
Table 10 lists common values for NCO_RDIV in 10-kHz frequency steps.
Table 10. Common NCO_RDIV Values (For 10-kHz Frequency Steps)
fCLK (MHz)
NCO_RDIV
2457.6
3840
1966.08
3072
1600
2500
1474.56
2304
1228.8
1920
7.3.6.1.5
NCO Phase Offset Setting
The NCO phase-offset setting for each NCO is set by the 16-bit register value PHASEAx and PHASEBx (where
x = 0 to 3). The value is left-justified into a 32-bit field and then added to the phase accumulator.
Use Equation 9 to calculate the phase offset in radians.
Φ(rad) = PHASEA/Bx × 2
–16 × 2 × π (x = 0 to 3)
(9)
7.3.6.1.6
NCO Phase Synchronization
The NCOs must be synchronized after setting or changing the value of FREQAx or FREQBx. NCO
synchronization is performed when the JESD204B link is initialized or by SYSREF, based on the settings of
NCO_SYNC_ILA and NCO_SYNC_NEXT. The procedures are as follows for the JESD204B initialization
procedure and the SYSREF procedure for both DC-coupled and AC-coupled SYSREF signals.
NCO synchronization using the JESD204B SYNC signal (SYNCSE or TMSTP±):
1. The device must be programmed for normal operation
2. Set NCO_SYNC_ILA to 1
3. Set JESD_EN to 0
4. Program FREQAx, FREQBx, PHASEAx, and PHASEBx to the desired settings
5. In the JESD204B receiver (logic device), deassert the SYNC signal by setting SYNC high
6. Set JESD_EN to 1
7. Assert the SYNC signal by setting SYNC low in the JESD204B receiver to start the code group
synchronization (CGS) process
8. After achieving CGS, deassert the SYNC signal by setting SYNC high at the same time for all ADCs to be
synchronized and verify that the SYNC setup and hold times are met (as specified in the Timing
Requirements table)
NCO synchronization using SYSREF (DC-coupled):
1. The device must be programmed for normal operation
2. Set JESD_EN to 1 to start the JESD204B link (the SYNC signal can respond as normal during the CGS
process)
3. Program FREQAx, FREQBx, PHASEAx, and PHASEBx to the desired settings
4. Verify that SYSREF is disabled (held low)
5. Arm NCO synchronization by setting NCO_SYNC_NEXT to 1
6. Issue a single SYSREF pulse to all ADCs to synchronize NCOs within all devices


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