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ADC12DJ2700 Datasheet(PDF) 45 Page - Texas Instruments

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Part No. ADC12DJ2700
Description  5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12DJ2700 Datasheet(HTML) 45 Page - Texas Instruments

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Sampled Input Signal
Internal Unadjusted
Device Clock
Internal SYSREF
(SPI register bit)
Internal Calibrated
Device Clock
Before calibration, device clock falling edge does
not align with SYSREF rising edge
After calibration, device clock falling edge
aligns with SYSREF rising edge
(SPI register bit)
Product Folder Links: ADC12DJ2700
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Copyright © 2018, Texas Instruments Incorporated
Figure 66 provides a timing diagram of the SYSREF calibration procedure. The optimized setup and hold times
are shown as tSU(OPT) and tH(OPT), respectively. Device clock and SYSREF are referred to as internal in this
diagram because the phase of the internal signals are aligned within the device and not to the external (applied)
phase of the device clock or SYSREF.
Figure 66. SYSREF Calibration Timing Diagram
When finished, the tAD adjust setting found by the automatic SYSREF calibration can be read from SRC_TAD in
the SYSREF calibration status register. After calibration, the system continues to use the calibrated tAD adjust
setting for operation until the system is powered down. However, if desired, the user can then disable the
SYSREF calibration and fine-tune the tAD adjust setting according to the systems needs. Alternatively, the use of
the automatic SYSREF calibration can be done at product test (or periodic recalibration) of the optimal tAD adjust
setting for each system. This value can be stored and written to the TAD register (TAD_INV, TAD_COARSE, and
TAD_FINE) upon system startup.
Do not run the SYSREF calibration when the ADC calibration (foreground or background) is running. If
background calibration is the desired use case, disable the background calibration when the SYSREF calibration
is used, then reenable the background calibration after TAD_DONE goes high. SYSREF_SEL in the clock control
register 0 must be set to 0 when using SYSREF calibration.
SYSREF calibration searches the TAD_COARSE delays using both noninverted (TAD_INV = 0) and inverted
clock polarity (TAD_INV = 1) to minimize the required TAD_COARSE setting in order to minimize loss on the
clock path to reduce aperture jitter (tAJ).
7.3.6 Digital Down Converters (Dual-Channel Mode Only)
After converting the analog voltage to a digital value, the digitized sample can either be sent directly to the
JESD204B interface block (DDC bypass) or sent to the digital down conversion (DDC) block for frequency
conversion and decimation (in dual-channel mode only). Frequency conversion and decimation allow a specific
frequency band to be selected and output in the digital data stream while reducing the effective data rate and
interface speed or width. The DDC is designed such that the digital processing does not degrade the noise
spectral density (NSD) performance of the ADC. Figure 67 illustrates the digital down converter for channel A of
the ADC12DJ2700. Channel B has the same structure with the input data selected by DIG_BIND_B and the
NCO selection mux controlled by pins NCOB[1:0] or through CSELB[1:0].

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