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ADC12DJ2700 Datasheet(PDF) 42 Page - Texas Instruments

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Part No. ADC12DJ2700
Description  5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12DJ2700 Datasheet(HTML) 42 Page - Texas Instruments

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CLK
SYSREF
R
f
f
10
F
K
n
u
u
u
u
42
ADC12DJ2700
SLVSEH9 – JANUARY 2018
www.ti.com
Product Folder Links: ADC12DJ2700
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Copyright © 2018, Texas Instruments Incorporated
The device clock is used as the sampling clock for the ADC core as well as the clocking for the digital processing
and serializer outputs. Use a low-noise (low jitter) device clock to maintain high signal-to-noise ratio (SNR) within
the ADC. In dual-channel mode, the analog input signal for each input is sampled on the rising edge of the
device clock. In single-channel mode, both the rising and falling edges of the device clock are used to capture
the analog signal to reduce the maximum clock rate required by the ADC. A noiseless aperture delay adjustment
(tAD adjust) allows the user to shift the sampling instance of the ADC in fine steps in order to synchronize multiple
ADC12DJ2700s or to fine-tune system latency. Duty cycle correction is implemented in the ADC12DJ2700 to
ease the requirements on the external device clock while maintaining high performance. Table 5 summarizes the
device clock interface in dual-channel mode and single-channel mode.
Table 5. Device Clock vs Mode of Operation
MODE OF OPERATION
SAMPLING RATE VS fCLK
SAMPLING INSTANT
Dual-channel mode
1 × fCLK
Rising edge
Single-channel mode
2 × fCLK
Rising and falling edge
SYSREF is a system timing reference used for JESD204B subclass-1 implementations of deterministic latency.
SYSREF is used to achieve deterministic latency and for multi-device synchronization. SYSREF must be
captured by the correct device clock edge in order to achieve repeatable latency and synchronization. The
ADC12DJ2700 includes SYSREF windowing and automatic SYSREF calibration to ease the requirements on the
external clocking circuits and to simplify the synchronization process. SYSREF can be implemented as a single
pulse or as a periodic clock. In periodic implementations, SYSREF must be equal to, or an integer division of, the
local multiframe clock frequency. Equation 2 is used to calculate valid SYSREF frequencies.
where
R and F are set by the JMODE setting (see Table 19)
fCLK is the device clock frequency (CLK±)
K is the programmed multiframe length (see Table 19 for valid K settings)
and n is any positive integer
(2)
7.3.5.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
The ADC12DJ2700 contains a delay adjustment on the device clock (sampling clock) input path, called tAD
adjust, that can be used to shift the sampling instance within the device in order to align sampling instances
among multiple devices or for external interleaving of multiple ADC12DJ2700s. Further, tAD adjust can be used
for automatic SYSREF calibration to simplify synchronization; see the Automatic SYSREF Calibration section.
Aperture delay adjustment is implemented in a way that adds no additional noise to the clock path, however a
slight degradation in aperture jitter (tAJ) is possible at large values of TAD_COARSE because of internal clock
path attenuation. The degradation in aperture jitter can result in minor SNR degradations at high input
frequencies (see tAJ in the Switching Characteristics table). This feature is programmed using TAD_INV,
TAD_COARSE, and TAD_FINE in the DEVCLK timing adjust ramp control register. Setting TAD_INV inverts the
input clock resulting in a delay equal to half the clock period. Table 6 summarizes the step sizes and ranges of
the TAD_COARSE and TAD_FINE variable analog delays. All three delay options are independent and can be
used in conjunction. All clocks within the device are shifted by the programmed tAD adjust amount, which results
in a shift of the timing of the JESD204B serialized outputs and affects the capture of SYSREF.
Table 6. tAD Adjust Adjustment Ranges
ADJUSTMENT PARAMETER
ADJUSTMENT STEP
DELAY SETTINGS
MAXIMUM DELAY
TAD_INV
1 / (fCLK × 2)
1
1 / (fCLK × 2)
TAD_COARSE
See tTAD(STEP) in the Switching
Characteristics table
256
See tTAD(MAX) in the Switching
Characteristics table
TAD_FINE
See tTAD(STEP) in the Switching
Characteristics table
256
See tTAD(MAX) in the Switching
Characteristics table


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