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ADC12DJ2700 Datasheet(PDF) 41 Page - Texas Instruments

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Part No. ADC12DJ2700
Description  5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12DJ2700 Datasheet(HTML) 41 Page - Texas Instruments

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SYSREF Capture
tAD Adjust
Clock Distribution
and Synchronization
(ADC cores, digital,
JESD204B, etc.)
CLK+
CLK-
SYSREF+
SYSREF-
SYSREF Windowing
Automatic
SYSREF
Calibration
SYSREF_POS
SYSREF_SEL
SRC_EN
Duty Cycle
Correction
Copyright © 2017, Texas Instruments Incorporated
41
ADC12DJ2700
www.ti.com
SLVSEH9 – JANUARY 2018
Product Folder Links: ADC12DJ2700
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Copyright © 2018, Texas Instruments Incorporated
Typically, the OVR_T0 threshold can be set near the full-scale value (228 for example). When the threshold is
triggered, a typical system can turn down the system gain to avoid clipping. The OVR_T1 threshold can be set
much lower. For example, the OVR_T1 threshold can be set to 64 (peak input voltage of
−12 dBFS). If the input
signal is strong, the OVR_T1 threshold is tripped occasionally. If the input is quite weak, the threshold is never
tripped. The downstream logic device monitors the OVR_T1 bit. If OVR_T1 stays low for an extended period of
time, then the system gain can be increased until the threshold is occasionally tripped (meaning the peak level of
the signal is above
−12 dBFS).
7.3.3.4 Code Error Rate (CER)
ADC cores can generate bit errors within a sample, often called code errors (CER) or referred to as sparkle
codes, resulting from metastability caused by non-ideal comparator limitations. The ADC12DJ2700 uses a
unique ADC architecture that inherently allows significant code error rate improvements from traditional pipelined
flash or successive approximation register (SAR) ADCs. The code error rate of the ADC12DJ2700 is multiple
orders of magnitude better than what can be achieved in alternative architectures at equivalent sampling rates
providing significant signal reliability improvements.
7.3.4 Timestamp
The TMSTP+ and TMSTP– differential input can be used as a time-stamp input to mark a specific sample based
on the timing of an external trigger event relative to the sampled signal. TIMESTAMP_EN (see the LSB control
bit output register) must be set in order to use the timestamp feature and output the timestamp data. When
enabled, the LSB of the 12-bit ADC digital output reports the status of the TMSTP± input. In effect, the 12-bit
output sample consists of the upper 11-bits of the 12-bit converter and the LSB of the 12-bit output sample is the
output of a parallel 1-bit converter (TMSTP±) with the same latency as the ADC core. In the 8-bit operating
modes, the LSB of the 8-bit output sample is used to output the timestamp status. The trigger must be applied to
the differential TMSTP+ and TMSTP– inputs. The trigger can be asynchronous to the ADC sampling clock and is
sampled at approximately the same time as the analog input. Timestamp cannot be used when a JMODE with
decimation is selected and instead SYSREF must be used to achieve synchronization through the JESD204B
subclass-1 method for achieving deterministic latency.
7.3.5 Clocking
The clocking subsystem of the ADC12DJ2700 has two input signals, device clock (CLK+, CLK–) and SYSREF
(SYSREF+, SYSREF–). Within the clocking subsystem there is a noiseless aperture delay adjustment (tAD
adjust), a clock duty cycle corrector, and a SYSREF capture block. Figure 65 shows the clocking subsystem.
Figure 65. ADC12DJ2700 Clocking Subsystem


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