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ADC12DJ2700 Datasheet(PDF) 40 Page - Texas Instruments

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Part No. ADC12DJ2700
Description  5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12DJ2700 Datasheet(HTML) 40 Page - Texas Instruments

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ADC12DJ2700
SLVSEH9 – JANUARY 2018
www.ti.com
Product Folder Links: ADC12DJ2700
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Copyright © 2018, Texas Instruments Incorporated
If the upper 8 bits of the absolute value equal or exceed the OVR_T0 or OVR_T1 thresholds during the
monitoring period, then the overrange bit associated with the threshold is set to 1, otherwise the overrange bit is
0. In dual-channel mode, the overrange status can be monitored on the ORA0 and ORA1 pins for channel A and
the ORB0 and ORB1 pins for channel B, where ORx0 corresponds to the OVR_T0 threshold and ORx1
corresponds to the OVR_T1 threshold. In single-channel mode, the overrange status for the OVR_T0 threshold
is determined by monitoring both the ORA0 and ORB0 outputs and the OVR_T1 threshold is determined by
monitoring both ORA1 and ORB1 outputs. In single-channel mode, the two outputs for each threshold must be
OR'd together to determine whether an overrange condition occurred. OVR_N can be used to set the output
pulse duration from the last overrange event. Table 3 lists the overrange pulse lengths for the various OVR_N
settings (see the overrange configuration register). In decimation modes (only in the JMODEs where CS = 1 in
Table 19), the overrange status is also embedded into the output data samples. For complex decimation modes,
the OVR_T0 threshold status is embedded as the LSB along with the upper 15 bits of every complex I sample
and the OVR_T1 threshold status is embedded as the LSB along with the upper 15 bits of every complex Q
sample. For real decimation modes, the OVR_T0 threshold status is embedded as the LSB of every even-
numbered sample and the OVR_T1 threshold status is embedded as the LSB of every odd-numbered sample.
Table 4 lists the outputs, related data samples, threshold settings, and the monitoring period equation. The
embedded overrange bit goes high if the associated channel exceeds the associated overrange threshold within
the monitoring period set by OVR_N. Use Table 4 to calculate the monitoring period.
Table 3. Overrange Monitoring Period for the ORA0, ORA1, ORB0, and ORB1 Outputs
OVR_N
OVERRANGE PULSE LENGTH SINCE LAST OVERRANGE
EVENT (DEVCLK Cycles)
0
8
1
16
2
32
3
64
4
128
5
256
6
512
7
1024
(1)
OVR_N is the monitoring period register setting.
Table 4. Threshold and Monitoring Period for Embedded Overrange Indicators in Dual-Channel
Decimation Modes
OVERRANGE
INDICATOR
ASSOCIATED
THRESHOLD
DECIMATION TYPE
OVERRANGE STATUS
EMBEDDED IN
MONITORING PERIOD
(ADC Samples)
ORA0
OVR_T0
Real decimation (JMODE 9)
Channel A even-
numbered samples
2OVR_N+1(1)
Complex down-conversion (JMODE
10-16, except JMODE 12)
Channel A in-phase (I)
samples
2OVR_N(1)
ORA1
OVR_T1
Real decimation (JMODE 9)
Channel A odd-
numbered samples
2OVR_N+1(1)
Complex down-conversion (JMODE
10-16, except JMODE 12)
Channel A quadrature
(Q) samples
2OVR_N(1)
ORB0
OVR_T0
Real decimation (JMODE 9)
Channel B even-
numbered samples
2OVR_N+1(1)
Complex down-conversion (JMODE
10-16, except JMODE 12)
Channel B in-phase (I)
samples
2OVR_N(1)
ORB1
OVR_T1
Real decimation (JMODE 9)
Channel B odd-
numbered samples
2OVR_N+1(1)
Complex down-conversion (JMODE
10-16, except JMODE 12)
Channel B quadrature
(Q) samples
2OVR_N(1)


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