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ADC12DJ2700 Datasheet(PDF) 4 Page - Texas Instruments

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Part No. ADC12DJ2700
Description  5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12DJ2700 Datasheet(HTML) 4 Page - Texas Instruments

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ADC12DJ2700
SLVSEH9 – JANUARY 2018
www.ti.com
Product Folder Links: ADC12DJ2700
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Copyright © 2018, Texas Instruments Incorporated
(1)
Powering down the high-speed data outputs (DA0± ... DA7±, DB0± ... DB7±) for extended times may reduce performance of the output
serializers, especially at high data rates. Powering down the serializers occurs when the PD pin is held high, the MODE register is
programmed to a value other than 0x00 or 0x01, the PD_ACH or PD_BCH registers settings are programmed to 1, or when the JMODE
register setting is programmed to a mode that uses less than the 16 total lanes that the device allows. For instance, JMODE 0 uses
eight total lanes and therefore the four highest-indexed lanes for each JESD204B link (DA4± ... DA7±, DB4± ... DB7±) are powered
down in this mode. When the PD pin is held high or the MODE register is programmed to a value other than 0x00 or 0x01, all output
serializers are powered down. When the PD_ACH or PD_BCH register settings are programmed to 1, the associated ADC channel and
lanes are powered down. To prevent unreliable operation, the PD pin and MODE register must only be used for brief periods of time to
measure temperature diode offsets and not used for long-term power savings. Furthermore, using a JMODE that uses fewer than 16
lanes results in unreliable operation of the unused lanes. If the system will never use the unused lanes during the lifetime of the device,
then the unused lanes do not cause issues and can be powered down. If the system may make use of the unused lanes at a later time,
the reliable operation of the serializer outputs can be maintained by enabling JEXTRA_A and JEXTRA_B, which results in the VD11
power consumption to increase and the output serializers to toggle.
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
A1, A2, A3
AGND
Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
A4
INA+
I
Channel A analog input positive connection. The differential full-scale input voltage is determined
by the FS_RANGE_A register (see the Full-Scale Voltage (VFS) Adjustment section). This input
is terminated to ground through a 50-Ω termination resistor. The input common-mode voltage is
typically be set to 0 V (GND) and must follow the recommendations in the Recommended
Operating Conditions table. This pin can be left disconnected if not used. Using INA± is
recommended in single-channel mode for optimized performance.
A5
INA–
I
Channel A analog input negative connection. See INA+ (pin A4) for detailed description. This
input is terminated to ground through a 50-Ω termination resistor. This pin can be left
disconnected if not used.
A6, A7
AGND
Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
A8
DA3+
O
High-speed serialized-data output for channel A, lane 3, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used. For information regarding reliable
serializer operation, see footnote (1) in the Pin Functions table.
A9
DA3–
O
High-speed serialized-data output for channel A, lane 3, negative connection. This pin can be left
disconnected if not used. For information regarding reliable serializer operation, see footnote (1) in
the Pin Functions table.
A10
DA2+
O
High-speed serialized-data output for channel A, lane 2, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used. For information regarding reliable
serializer operation, see footnote (1) in the Pin Functions table.
A11
DA2–
O
High-speed serialized-data output for channel A, lane 2, negative connection. This pin can be left
disconnected if not used. For information regarding reliable serializer operation, see footnote (1) in
the Pin Functions table.
A12
DGND
Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
B1
TMSTP+
I
Timestamp input positive connection or differential JESD204B SYNC positive connection. This
input is a timestamp input, used to mark a specific sample, when TIMESTAMP_EN is set to 1.
This differential input is used as the JESD204B SYNC signal input when SYNC_SEL is set 1.
This input can be used as both a timestamp and differential SYNC input at the same time,
allowing feedback of the SYNC signal using the timestamp mechanism. TMSTP± uses active low
signaling when used as a JESD204B SYNC. For additional usage information, see the
Timestamp section.
TMSTP_RECV_EN must be set to 1 to use this input. This differential input (TMSTP+ to
TMSTP–) has an internal untrimmed 100-Ω differential termination and can be AC-coupled when
TMSTP_LVPECL_EN is set to 0. The termination changes to 50 Ω to ground on each input pin
(TMSTP+ and TMSTP–) and can be DC coupled when TMSTP_LVPECL_EN is set to 1. This pin
is not self-biased and therefore must be externally biased for both AC- and DC-coupled
configurations. The common-mode voltage must be within the range provided in the
Recommended Operating Conditions table when both AC and DC coupled. This pin can be left
disconnected and disabled (TMSTP_RECV_EN = 0) if SYNCSE is used for JESD204B SYNC
and timestamp is not required.
B2, B3, B4,
B5, B6, B7
AGND
Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.


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