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ADC12DJ2700 Datasheet(PDF) 39 Page - Texas Instruments

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Part No. ADC12DJ2700
Description  5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12DJ2700 Datasheet(HTML) 39 Page - Texas Instruments

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IN
FS
N
Code
V
V
2
39
ADC12DJ2700
www.ti.com
SLVSEH9 – JANUARY 2018
Product Folder Links: ADC12DJ2700
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Copyright © 2018, Texas Instruments Incorporated
7.3.2.3 Analog Input Offset Adjust
The input offset voltage for each input can be adjusted through the OADJ_x_INy registers (registers 0x08A and
0x095), where x represents the ADC core (A, B, or C) and y represents the analog input (INA± or INB±). The
adjustment range is approximately 28 mV to –28 mV differential. See the Calibration Modes and Trimming
section for more information.
7.3.3 ADC Core
The ADC12DJ2700 consists of a total of six ADC cores. The cores are interleaved for higher sampling rates and
swapped on-the-fly for calibration as required by the operating mode. This section highlights the theory and key
features of the ADC cores.
7.3.3.1 ADC Theory of Operation
The differential voltages at the analog inputs are captured by the rising edge of CLK± in dual-channel mode or by
the rising and falling edges of CLK± in single-channel mode. After capturing the input signal, the ADC converts
the analog voltage to a digital value by comparing the voltage to the internal reference voltage. If the voltage on
INA– or INB– is higher than the voltage on INA+ or INB+, respectively, then the digital output is a negative 2's
complement value. If the voltage on INA+ or INB+ is higher than the voltage on INA– or INB–, respectively, then
the digital output is a positive 2's complement value. Equation 1 can calculate the differential voltage at the input
pins from the digital output.
where
Code is the signed decimation output code (for example, –2048 to +2047)
N is the ADC resolution
and VFS is the full-scale input voltage of the ADC as specified in the Recommended Operating Conditions
table, including any adjustment performed by programming FS_RANGE_A or FS_RANGE_B
(1)
7.3.3.2 ADC Core Calibration
ADC core calibration is required to optimize the analog performance of the ADC cores. Calibration must be
repeated when operating conditions change significantly, namely temperature, in order to maintain optimal
performance. The ADC12DJ2700 has a built-in calibration routine that can be run as a foreground operation or a
background operation. Foreground operation requires ADC downtime, where the ADC is no longer sampling the
input signal, to complete the process. Background calibration can be used to overcome this limitation and allow
constant operation of the ADC. See the Calibration Modes and Trimming section for detailed information on each
mode.
7.3.3.3 ADC Overrange Detection
To ensure that system gain management has the quickest possible response time, a low-latency configurable
overrange function is included. The overrange function works by monitoring the converted 12-bit samples at the
ADC to quickly detect if the ADC is near saturation or already in an overrange condition. The absolute value of
the upper 8 bits of the ADC data are checked against two programmable thresholds, OVR_T0 and OVR_T1.
These thresholds apply to both channel A and channel B in dual-channel mode. Table 2 lists how an ADC
sample is converted to an absolute value for a comparison of the thresholds.
Table 2. Conversion of ADC Sample for Overrange Comparison
ADC SAMPLE
(Offset Binary)
ADC SAMPLE
(2's Complement)
ABSOLUTE VALUE
UPPER 8 BITS USED FOR
COMPARISON
1111 1111 1111 (4095)
0111 1111 1111 (+2047)
111 1111 1111 (2047)
1111 1111 (255)
1111 1111 0000 (4080)
0111 1111 0000 (+2032)
111 1111 0000 (2032)
1111 1110 (254)
1000 0000 0000 (2048)
0000 0000 0000 (0)
000 0000 0000 (0)
0000 0000 (0)
0000 0001 0000 (16)
1000 0001 0000 (–2032)
111 1111 0000 (2032)
1111 1110 (254)
0000 0000 0000 (0)
1000 0000 0000 (–2048)
111 1111 1111 (2047)
1111 1111 (255)


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