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ADC12DJ2700 Datasheet(PDF) 36 Page - Texas Instruments

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Part No. ADC12DJ2700
Description  5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12DJ2700 Datasheet(HTML) 36 Page - Texas Instruments

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ADC12DJ2700
SLVSEH9 – JANUARY 2018
www.ti.com
Product Folder Links: ADC12DJ2700
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Copyright © 2018, Texas Instruments Incorporated
7 Detailed Description
7.1 Overview
The ADC12DJ2700 is an RF-sampling, giga-sample analog-to-digital converter (ADC) that can directly sample
input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC12DJ2700 can sample up to
2700 MSPS and up to 5400 MSPS in single-channel mode. Programmable tradeoffs in channel count (dual-
channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets
the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input
bandwidth (–3 dB) of 8.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-
channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.
Time interleaving is achieved internally through four active cores. In dual-channel mode, two cores are
interleaved per channel to increase the sample rate to twice the core sample rate. In single-channel mode, all
four cores are time interleaved to increase the sample rate to 4x the core sample rate. Either input can be used
in single-channel mode, however performance is optimized for INA±. The user provides a clock at twice the ADC
core sample rate and the generation of the clocks for the interleaved cores is done internally for both single-
channel mode and dual-channel mode. The ADC12DJ2700 also provides foreground and background calibration
options to match the gain and offset between cores to minimize spurious artifacts from interleaving.
This ADC core is followed by a configurable digital down converter (DDC) block. The DDC block provides a
range of decimation settings that allow the device to work in ultra-wideband, wideband, and more-narrow-band
receive systems. Additionally, a single ADC channel (in dual-channel mode) can be muxed to separate DDC
blocks for multi-band receive applications.
The ADC12DJ2700 uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1
compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to
12.8 Gbps and can be configured to trade-off bit rate and number of lanes. Innovative synchronization features,
including noiseless aperture delay (TAD) adjustment and SYSREF windowing, simplify system design for phased
array radar and multiple-input-multiple-output (MIMO) communications. Optional DDCs in dual-channel mode
allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal
(complex decimation modes only).


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