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ADC12DJ2700 Datasheet(PDF) 24 Page - Texas Instruments

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Part No. ADC12DJ2700
Description  5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12DJ2700 Datasheet(HTML) 24 Page - Texas Instruments

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CLK+
CLK±
DA0+/±
(2)
SYSREF+
SYSREF±
/R
SYNCSE
(SYNC_SEL = 0)
tH(SYNCSE)
tSU(SYNCSE)
tTX
Start of ILAS
LMFC
(1)
(Internal)
One multi-frame
One multi-frame
TMSTP+/±
(SYNC_SEL = 1)
CLK+
CLK±
DA0+/±
(1)
tAD
tADC
SYSREF+
SYSREF±
tSU(SYSREF)
tTX
S0
S1
S2
tCLK
S0
S1
S2
tH(SYSREF)
Start of Multi-Frame
24
ADC12DJ2700
SLVSEH9 – JANUARY 2018
www.ti.com
Product Folder Links: ADC12DJ2700
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Copyright © 2018, Texas Instruments Incorporated
Switching Characteristics (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0xA000), input signal applied to INA± in single-channel modes, fIN = 248 MHz, AIN = –1 dBFS, fCLK =
maximum rated clock frequency, filtered 1-VPP sine-wave clock, JMODE = 1, and background calibration (unless otherwise
noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range
provided in the Recommended Operating Conditions table
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SERIAL PROGRAMMING INTERFACE (SDO)
t(OZD)
Maximum delay from the falling edge of the 16th SCLK cycle during read
operation for SDO transition from tri-state to valid data
7
ns
t(ODZ)
Maximum delay from the SCS rising edge for SDO transition from valid
data to tri-state
7
ns
t(OD)
Maximum delay from the falling edge of the 16th SCLK cycle during read
operation to SDO valid
12
ns
(1)
Only the SerDes lane DA0± is shown, but DA0± is representative of all lanes. The number of output lanes used and
bit-packing format is dependent on the programmed JMODE value.
Figure 1. ADC Timing Diagram
(2)
It is assumed that the internal LMFC is aligned with the rising edge of CLK± that captures the SYSREF± high value.
(3)
Only SerDes lane DA0± is shown, but DA0± is representative of all lanes. All lanes output /R at approximately the
same point in time. The number of lanes is dependent on the programmed JMODE value.
Figure 2. SYNCSE and TMSTP± Timing Diagram for NCO Synchronization


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