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ADC12DJ2700 Datasheet(PDF) 22 Page - Texas Instruments

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Part No. ADC12DJ2700
Description  5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12DJ2700 Datasheet(HTML) 22 Page - Texas Instruments

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ADC12DJ2700
SLVSEH9 – JANUARY 2018
www.ti.com
Product Folder Links: ADC12DJ2700
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
(1)
tAJ increases because of additional attenuation on the internal clock path.
6.10 Switching Characteristics
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0xA000), input signal applied to INA± in single-channel modes, fIN = 248 MHz, AIN = –1 dBFS, fCLK =
maximum rated clock frequency, filtered 1-VPP sine-wave clock, JMODE = 1, and background calibration (unless otherwise
noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range
provided in the Recommended Operating Conditions table
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DEVICE (SAMPLING) CLOCK (CLK+, CLK–)
tAD
Sampling (aperture) delay from the
CLK± rising edge (dual-channel
mode) or rising and falling edge
(single-channel mode) to sampling
instant
TAD_COARSE = 0x00, TAD_FINE
= 0x00, and TAD_INV = 0
360
ps
tTAD(MAX)
Maximum tAD adjust programmable
delay, not including clock inversion
(TAD_INV = 0)
Coarse adjustment
(TAD_COARSE = 0xFF)
289
ps
Fine adjustment (TAD_FINE =
0xFF)
4.9
ps
tTAD(STEP)
tAD adjust programmable delay step
size
Coarse adjustment
(TAD_COARSE)
1.13
ps
Fine adjustment (TAD_FINE)
19
fs
tAJ
Aperture jitter, rms
Minimum tAD adjust coarse setting
(TAD_COARSE = 0x00, TAD_INV
= 0)
50
fs
Maximum tAD adjust coarse setting
(TAD_COARSE = 0xFF) excluding
TAD_INV (TAD_INV = 0)
70(1)
SERIAL DATA OUTPUTS (DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–)
fSERDES
Serialized output bit rate
1
12.8
Gbps
UI
Serialized output unit interval
78.125
1000
ps
tTLH
Low-to-high transition time
(differential)
20% to 80%, PRBS-7 test pattern,
12.8 Gbps, SER_PE = 0x04
37
ps
tTHL
High-to-low transition time
(differential)
20% to 80%, PRBS-7 test pattern,
12.8 Gbps, SER_PE = 0x04
37
ps
DDJ
Data dependent jitter, peak-to-peak
PRBS-7 test pattern, 12.8 Gbps,
SER_PE = 0x04, JMODE = 2
7.8
ps
RJ
Random jitter, RMS
PRBS-7 test pattern, 12.8 Gbps,
SER_PE = 0x04, JMODE = 2
1.1
ps
TJ
Total jitter, peak-to-peak, with
gaussian portion defined with respect
to a BER = 1e-15 (Q = 7.94)
PRBS-7 test pattern, 12.8 Gbps,
SER_PE = 0x04, JMODE = 0, 2
25
ps
PRBS-7 test pattern, 6.4 Gbps,
SER_PE = 0x04, JMODE = 1, 3
21
PRBS-7 test pattern, 8 Gbps,
SER_PE = 0x04, JMODE = 4, 5, 6,
7
28
PRBS-7 test pattern, 8 Gbps,
SER_PE = 0x04, JMODE = 9
35
PRBS-7 test pattern, 8 Gbps,
SER_PE = 0x04, JMODE = 10, 11
40
PRBS-7 test pattern, 3.2 Gbps,
SER_PE = 0x04, JMODE = 12
26
PRBS-7 test pattern, 8 Gbps,
SER_PE = 0x04, JMODE = 13, 14
39
PRBS-7 test pattern, 8 Gbps,
SER_PE = 0x04, JMODE = 15, 16
34


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