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ADC12DJ2700 Datasheet(PDF) 21 Page - Texas Instruments

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Part No. ADC12DJ2700
Description  5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12DJ2700 Datasheet(HTML) 21 Page - Texas Instruments

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ADC12DJ2700
www.ti.com
SLVSEH9 – JANUARY 2018
Product Folder Links: ADC12DJ2700
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Copyright © 2018, Texas Instruments Incorporated
(1)
Unless functionally limited to a smaller range in Table 19 based on programmed JMODE.
(2)
Use SYSREF_POS to select an optimal SYSREF_SEL value for the SYSREF capture, see the SYSREF Position Detector and
Sampling Position Selection (SYSREF Windowing) section for more information on SYSREF windowing. The invalid region, specified by
tINV(SYSREF), indicates the portion of the CLK± period (tCLK), as measured by SYSREF_SEL, that may result in a setup and hold violation.
Verify that the timing skew between SYSREF± and CLK± over system operating conditions from the nominal conditions (that used to
find optimal SYSREF_SEL) does not result in the invalid region occurring at the selected SYSREF_SEL position in SYSREF_POS,
otherwise a temperature dependent SYSREF_SEL selection may be needed to track the skew between CLK± and SYSREF±.
6.9 Timing Requirements
MIN
NOM
MAX
UNIT
DEVICE (SAMPLING) CLOCK (CLK+, CLK–)
fCLK
Input clock frequency (CLK+, CLK–), both single-channel and dual-channel
modes(1)
800
2700
MHz
SYSREF (SYSREF+, SYSREF–)
tINV(SYSREF)
Width of invalid SYSREF capture region of CLK± period, indicating setup or
hold time violation, as measured by SYSREF_POS status register(2)
48
ps
tINV(TEMP)
Drift of invalid SYSREF capture region over temperature, positive number
indicates a shift toward MSB of SYSREF_POS register
0
ps/°C
tINV(VA11)
Drift of invalid SYSREF capture region over VA11 supply voltage, positive
number indicates a shift toward MSB of SYSREF_POS register
0.36
ps/mV
tSTEP(SP)
Delay of SYSREF_POS LSB
SYSREF_ZOOM = 0
77
ps
SYSREF_ZOOM = 1
24
t(PH_SYS)
Minimum SYSREF± assertion duration after SYSREF± rising edge event
4
ns
t(PL_SYS)
Minimum SYSREF± de-assertion duration after SYSREF± falling edge
event
1
ns
JESD204B SYNC TIMING (SYNCSE OR TMSTP±)
tH(SYNCSE)
Minimum hold time from multiframe boundary
(SYSREF rising edge captured high) to de-
assertion of JESD204B SYNC signal (SYNCSE if
SYNC_SEL = 0 or TMSTP± if SYNC_SEL = 1) for
NCO synchronization (NCO_SYNC_ILA = 1)
JMODE = 0, 2, 4, 6,
10, 13, or 15
21
tCLK
cycles
JMODE = 1, 3, 5, 7, 9,
11, 14, or 16
17
JMODE = 12, 17, or 18
9
tSU(SYNCSE)
Minimum setup time from de-assertion of
JESD204B SYNC signal (SYNCSE if SYNC_SEL
= 0 or TMSTP± if SYNC_SEL = 1) to multiframe
boundary (SYSREF rising edge captured high) for
NCO synchronization (NCO_SYNC_ILA = 1)
JMODE = 0, 2, 4, 6,
10, 13, or 15
–2
tCLK
cycles
JMODE = 1, 3, 5, 7, 9,
11, 14, or 16
2
JMODE = 12, 17, or 18
10
t(SYNCSE)
SYNCSE minimum assertion time to trigger link resynchronization
4
Frames
SERIAL PROGRAMMING INTERFACE (SCLK, SDI, SCS)
fCLK(SCLK)
Maximum serial clock frequency
15.625
MHz
t(PH)
Minimum serial clock high value pulse duration
32
ns
t(PL)
Minimum serial clock low value pulse duration
32
ns
tSU(SCS)
Minimum setup time from SCS to rising edge of SCLK
30
ns
tH(SCS)
Minimum hold time from rising edge of SCLK to SCS
3
ns
tSU(SDI)
Minimum setup time from SDI to rising edge of SCLK
30
ns
tH(SDI)
Minimum hold time from rising edge of SCLK to SDI
3
ns


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