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AD7715 Datasheet(PDF) 25 Page - Analog Devices |
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AD7715 Datasheet(HTML) 25 Page - Analog Devices |
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25 / 41 page  AD7715 Data Sheet Rev. E | Page 24 of 40 System Calibration System calibration allows the AD7715 to compensate for system gain and offset errors as well as its own internal errors. System calibration performs the same slope factor calculations as self calibration but uses voltage values presented by the system to the AIN inputs for the zero- and full-scale points. full system calibration requires a two step process, a zero-scale system calibration followed by a full-scale system calibration. For a full system calibration, the zero-scale point must be presented to the converter first. It must be applied to the converter before the calibration step is initiated and remain stable until the step is complete. Once the system zero scale voltage has been set up, a zero-scale system calibration is then initiated by writing the appropriate values (1, 0) to the MD1 and MD0 bits of the setup register. The zero-scale system calibration is performed at the selected gain. The duration of the calibration is 3 × 1/output rate. At this time, the MD1 and MD0 bits in the setup register return to 0, 0. This gives the earliest indication that the calibration sequence is complete. The DRDY line goes high when calibration is initiated and does not return low until there is a valid new word in the data register. The duration time from the calibration command being issued to DRDY going low is 4 × 1/output rate as the part performs a normal conversion on the AIN voltage before DRDY goes low. If DRDY is low before (or goes low during) the calibration command write to the setup register, it may take up to one modulator cycle (MCLK IN/128) before DRDY goes high to indicate that calibration is in progress. Therefore, DRDY should be ignored for up to one modulator cycle after the last bit is written to the setup register in the calibration command. After the zero-scale point is calibrated, the full-scale point is applied to AIN and the second step of the calibration process is initiated by again writing the appropriate values (1, 1) to MD1 and MD0. Again, the full-scale voltage must be set up before the calibration is initiated and it must remain stable throughout the calibration step. The full-scale system calibration is performed at the selected gain. The duration of the calibration is 3 × 1/output rate. At this time, the MD1 and MD0 bits in the setup register return to 0, 0. This gives the earliest indication that the calibration sequence is complete. The DRDY line goes high when calibration is initiated and does not return low until there is a valid new word in the data register. The duration time from the calibration command being issued to DRDY going low is 4 × 1/output rate as the part performs a normal conversion on the AIN voltage before DRDY goes low. If DRDY is low before (or goes low during) the calibration command, write to the setup register, it may take up to one modulator cycle (MCLK IN/128) before DRDY goes high to indicate that calibration is in progress. Therefore, DRDY should be ignored for up to one modulator cycle after the last bit is written to the setup register in the calibration command. In the unipolar mode, the system calibration is performed between the two endpoints of the transfer function. In the bipolar mode, it is performed between midscale (zero differential voltage) and positive full scale. The fact that the system calibration is a two-step calibration offers another feature. After the sequence of a full system cali- bration has been completed, additional offset or gain calibrations can be performed by themselves to adjust the system zero reference point or the system gain. Calibrating one of the parameters, either system offset or system gain, does not affect the other parameter. System calibration can also be used to remove any errors from source impedances on the analog input when the part is used in unbuffered mode. A simple R, C antialiasing filter on the front end may introduce a gain error on the analog input voltage but the system calibration can be used to remove this error. Span and Offset Limits Whenever a system calibration mode is used, there are limits on the amount of offset and span which can be accommodated. The overriding requirement in determining the amount of offset and gain that can be accommodated by the part is the requirement that the positive full-scale calibration limit is ≤ 1.05 × VREF/GAIN. This allows the input range to go 5% above the nominal range. The in-built headroom in the analog modulator of the AD7715 ensures that the part still operates correctly with a positive full-scale voltage which is 5% beyond the nominal. The range of input span in both the unipolar and bipolar modes has a minimum value of 0.8 × VREF/GAIN and a maximum value of 2.1 × VREF/GAIN. However, the span (which is the difference between the bottom of the AD7715’s input range and the top of its input range) must take into account the limitation on the positive full-scale voltage. The amount of offset that can be accommodated depends on whether the unipolar or bipolar mode is being used. Once again, the offset must take into account the limitation on the positive full-scale voltage. In unipolar mode, there is considerable flexibility in handling negative (with respect to AIN(−)) offsets. In both unipolar and bipolar modes, the range of positive offsets which can be handled by the part depends on the selected span. Therefore, in determining the limits for system zero-scale and full-scale calibrations, the user has to ensure that the offset range plus the span range does exceed 1.05 × VREF/GAIN. This is best illustrated by looking at the following examples. |
Similar Part No. - AD7715_17 |
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Similar Description - AD7715_17 |
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