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AD7715 Datasheet(PDF) 20 Page - Analog Devices

Part No. AD7715
Description  16-Bit, Sigma-Delta ADC
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7715 Datasheet(HTML) 20 Page - Analog Devices

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Data Sheet
AD7715
Rev. E | Page 19 of 40
CIRCUIT DESCRIPTION
The AD7715 is a Σ-Δ ADC with on-chip digital filtering,
intended for the measurement of wide dynamic range, low
frequency signals such as those in industrial control or process
control applications. It contains a Σ-Δ (or charge-balancing)
ADC, a calibration microcontroller with on-chip static RAM, a
clock oscillator, a digital filter, and a bidirectional serial commu-
nications port. The part consumes only 450 μA of power supply
current, making it ideal for battery-powered or loop-powered
instruments. The part comes in two versions, the AD7715-5
which is specified for operation from a nominal 5 V analog supply
(AVDD) and the AD7715-3 which is specified for operation from
a nominal 3.3 V analog supply. Both versions can be operated
with a digital supply (DVDD) voltage of 3.3 V or 5 V.
The part contains a programmable-gain fully differential analog
input channel. The selectable gains on this input are 1, 2, 32,
and 128 allowing the part to accept unipolar signals of between
0 mV to 20 mV and 0 V to 2.5 V or bipolar signals in the range
from ±20 mV to ±2.5 V when the reference input voltage equals
2.5 V. With a reference voltage of 1.25 V, the input ranges are
from 0 mV to 10 mV to 0 V to +1.25 V in unipolar mode and
from ±10 mV to ±1.25 V in bipolar mode. Note that the bipolar
ranges are with respect to AIN(−) and not with respect to
AGND.
The input signal to the analog input is continuously sampled at
a rate determined by the frequency of the master clock, MCLK
IN, and the selected gain. A charge-balancing ADC (Σ-Δ mod-
ulator) converts the sampled signal into a digital pulse train whose
duty cycle contains the digital information. The programmable
gain function on the analog input is also incorporated in this Σ-Δ
modulator with the input sampling frequency being modified
to give the higher gains. A sinc3 digital low-pass filter processes
the output of the Σ-Δ modulator and updates the output register
at a rate determined by the first notch frequency of this filter.
The output data can be read from the serial port randomly or
periodically at any rate up to the output register update rate.
The first notch of this digital filter (and therefore its –3 dB
frequency) can be programmed via the setup register bits, FS0
and FS1. With a master clock frequency of 2.4576 MHz, the
programmable range for this first notch frequency is from 50 Hz
to 500 Hz giving a programmable range for the −3 dB frequency
of 13.1 Hz to 131 Hz. With a master clock frequency of 1 MHz,
the programmable range for this first notch frequency is from
20 Hz to 200 Hz giving a programmable range for the −3 dB
frequency of 5.24 Hz to 52.4 Hz.
The basic connection diagram for the AD7715-5 is shown in
Figure 4. This shows both the AVDD and DVDD pins of the AD7715
being driven from the analog 5 V supply. Some applications
have AVDD and DVDD driven from separate supplies. An AD780,
precision 2.5 V reference, provides the reference source for the
part. On the digital side, the part is configured for three-wire
operation with CS tied to DGND. A quartz crystal or ceramic
resonator provides the master clock source for the part. In most
cases, it is necessary to connect capacitors on the crystal or
resonator to ensure that it does not oscillate at overtones of its
fundamental operating frequency. The values of capacitors vary
depending on the manufacturer’s specifications.
SCLK
MCLK IN
DGND
DVDD
MCLK OUT
DIN
DOUT
AGND
AIN(+)
AIN(–)
REF IN(+)
REF IN(–)
AVDD
AD7715
ANALOG
GROUND
ANALOG
GROUND
DIFFERENTIAL
ANALOG INPUT
VOUT
VIN
GND
AD780
ANALOG
5V SUPPLY
DATA
READY
RECEIVE
(READ)
SERIAL
DATA
SERIAL
CLOCK
CRYSTAL OR
CERAMIC
RESONATOR
5V
10µF
0.1µF
10µF
0.1µF
0.1µF
ANALOG
5V SUPPLY
RESET
CS
DRDY
Figure 4. AD7715-5 Basic Connection Diagram
ANALOG INPUT
Analog Input Ranges
The AD7715 contains a differential analog input pair AIN(+)
and AIN(−). This input pair provides a programmable-gain,
differential input channel which can handle either unipolar or
bipolar input signals. It should be noted that the bipolar input
signals are referenced to the respective AIN(−) input of the
input pair.
In unbuffered mode, the common-mode range of the input is
from AGND to AVDD provided that the absolute value of the
analog input voltage lies between AGND − 30 mV and AVDD +
30 mV. This means that in unbuffered mode the part can handle
both unipolar and bipolar input ranges for all gains. In buffered
mode, the analog inputs can handle much larger source imped-
ances but the absolute input voltage range is restricted to between
AGND + 50 mV to AVDD − 1.5 V, which also places restrictions
on the common-mode range. This means that in buffered mode
there are some restrictions on the allowable gains for bipolar
input ranges. Care must be taken in setting up the common-
mode voltage and input voltage range so that the above limits
are not exceeded, otherwise there is a degradation in linearity
performance.


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