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AD7715 Datasheet(PDF) 7 Page - Analog Devices

Part # AD7715
Description  16-Bit, Sigma-Delta ADC
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7715 Datasheet(HTML) 7 Page - Analog Devices

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AD7715
Data Sheet
Rev. E | Page 6 of 40
Parameter1
Min
Typ
Max
Unit
Conditions/Comments
LOGIC OUTPUTS (Including MCLK OUT)
VOL, Output Low Voltage
0.4
V
ISINK = 100 µA except for MCLK OUT12
VOH, Output High Voltage
DVDD − 0.6
V
ISOURCE = 100 µA except for MCLK OUT12
Floating State Leakage Current
±10
µA
Floating State Output Capacitance13
9
pF
Data Output Coding
Binary
Unipolar mode
Offset binary
Bipolar mode
1
Temperature range as follows: A version, −40°C to +85°C.
2
A calibration is effectively a conversion, so these errors are of the order of the conversion noise shown in Table 15 to Table 22. This applies after calibration at the
temperature of interest.
3
Recalibration at any temperature removes these drift errors.
4
Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar and bipolar input ranges.
5
Full-scale drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar input ranges.
6
Gain error does not include zero-scale errors. It is calculated as full-scale error–unipolar offset error for unipolar ranges and Full-Scale Error–Bipolar Zero Error for
bipolar ranges.
7
Gain error drift does not include unipolar offset drift/bipolar zero drift. It is effectively the drift of the part if zero scale calibrations only were performed.
8
These numbers are guaranteed by design and/or characterization.
9
This common-mode voltage range is allowed provided that the input voltage on AIN(+) or AIN(−) does not go more positive than AVDD + 30 mV or go more negative
than AGND − 30 mV.
10
The analog input voltage range on AIN(+) is given here with respect to the voltage on AIN(−). The absolute voltage on the analog inputs should not go more positive
than AVDD + 30 mV or go more negative than AGND − 30 mV.
11
VREF = REF IN(+) − REF IN(−).
12
These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load.
13
Sample tested at 25°C to ensure compliance.


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