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AD7715 Datasheet(PDF) 6 Page - Analog Devices

Part No. AD7715
Description  16-Bit, Sigma-Delta ADC
Download  41 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7715 Datasheet(HTML) 6 Page - Analog Devices

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Data Sheet
AD7715
Rev. E | Page 5 of 40
AD7715-3
AVDD = 3 V, DVDD = 3 V, REF IN (+) = 1.25 V; REF IN(−) = AGND; fCLK IN = 2.4576 MHz, unless otherwise noted. All specifications TMIN
to TMAX, unless otherwise noted.
Table 2.
Parameter1
Min
Typ
Max
Unit
Conditions/Comments
STATIC PERFORMANCE
No Missing Codes
16
Bits
Guaranteed by design; filter notch ≤ 60 Hz
Output Noise
See Table 18 to Table 22
Depends on filter cutoffs and selected gain
Integral Nonlinearity
±0.0015
% of FSR
Filter notch ≤ 60 Hz
Unipolar Offset Error2
See Table 15 to Table 22
Unipolar Offset Drift3
0.2
μV/°C
Bipolar Zero Error2
See Table 15 to Table 22
Bipolar Zero Drift3
0.2
μV/°C
Positive Full-Scale Error2, 4
See Table 15 to Table 22
Full-Scale Drift3, 5
0.2
μV/°C
Gain Error2, 6
See Table 15 to Table 22
Gain Drift3, 7
0.2
ppm of
FSR/°C
Bipolar Negative Full-Scale Error2
±0.003
% of FSR
Typically ±0.0004%
Bipolar Negative Full-Scale Drift3
1
μV/°C
For gains of 1 and 2
0.6
μV/°C
For gains of 32 and 128
ANALOG INPUTS/REFERENCE INPUTS
Specifications for AIN and REF IN unless noted
Input Common-Mode Rejection
(CMR)
90
dB
At dc; tpically 102 dB
Normal-Mode 50 Hz Rejection8
98
dB
For filter notches of 25 Hz, 50 Hz, ±0.02 × fNOTCH
Normal-Mode 60 Hz Rejection8
98
dB
For filter notches of 20 Hz, 60 Hz, ±0.02 × fNOTCH
Common-Mode 50 Hz Rejection8
150
dB
For filter notches of 25 Hz, 50 Hz, ±0.02 × fNOTCH
Common-Mode 60 Hz Rejection8
150
dB
For filter notches of 20 Hz, 60 Hz, ±0.02 × fNOTCH
Common-Mode Voltage Range9
AGND
AVDD
V
AIN for BUF bit of setup register = 0 and REF IN
Absolute AIN/REF IN Voltage8
AGND − 0.03
AVDD + 0.03
V
AIN for BUF bit of setup register = 0 and REF IN
Absolute/Common-Mode AIN
Voltage9
AGND + 0.05
AVDD − 1.5
V
BUF bit of setup register = 1
AIN DC Input Current8
1
nA
AIN Sampling Capacitance8
10
pF
AIN Differential Voltage Range10
0 to +VREF/GAIN11
nom
Unipolar input range (
B/U bit of setup register = 1)
±VREF/GAIN
nom
Bipolar input range (
B/U bit of setup register = 0)
AIN Input Sampling Rate, fS
GAIN × fCLK IN/64
For gains of 1 and 2
fCLK IN/8
For gains of 32 and 128
REF IN(+) − REF IN(−) Voltage
1.25
V nom
±1% for specified performance; functional with
lower VREF
REF IN Input Sampling Rate, fS
fCLK IN/64
LOGIC INPUTS
Input Current
±10
μA
All Inputs Except MCLK IN
VINL, Input Low Voltage
0.8
V
VINH, Input High Voltage
2.0
V
MCLK IN Only
VINL, Input Low Voltage
0.4
V
VINH, Input High Voltage
2.5
V


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