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AD7715 Datasheet(PDF) 31 Page - Analog Devices |
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AD7715 Datasheet(HTML) 31 Page - Analog Devices |
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31 / 41 page  AD7715 Data Sheet Rev. E | Page 30 of 40 Figure 8 and Figure 9 show timing diagrams for interfacing to the AD7715 with CS used to decode the part. Figure 8 is for a read operation from the AD7715’s output shift register, while Figure 9 shows a write operation to the input shift register. It is possible to read the same data twice from the output register even though the DRDY line returns high after the first read operation. Take care, however, to ensure that the read operations have been completed before the next output update is about to take place. The AD7715 serial interface can operate in three-wire mode by tying the CS input low. In this case, the SCLK, DIN and DOUT lines are used to communicate with the AD7715 and the status of DRDY can be obtained by interrogating the MSB of the com- munications register. This scheme is suitable for interfacing to microcontrollers. If CS is required as a decoding signal, it can be generated from a port bit. For microcontroller interfaces, it is recommended that the SCLK idles high between data transfers. The AD7715 can also be operated with CS used as a frame synchronization signal. This scheme is suitable for DSP interfaces. In this case, the first bit (MSB) is effectively clocked out by CS because CS would normally occur after the falling edge of SCLK in DSPs. The SCLK can continue to run between data transfers provided the timing numbers are obeyed. The serial interface can be reset by exercising the RESET input on the part. It can also be reset by writing a series of 1s on the DIN input. If a Logic 1 is written to the AD7715 DIN line for at least 32 serial clock cycles, the serial interface is reset. This ensures that in three-wire systems that if the interface gets lost either via a software error or by some glitch in the system, it can be reset back into a known state. This state returns the interface to where the AD7715 is expecting a write operation to its com- munications register. This operation in itself does not reset the contents of any registers, but because the interface was lost, the information that was written to any of the registers is unknown and it is advisable to set up all registers again. Some microprocessor or microcontroller serial interfaces have a single serial data line. In this case, it is possible to connect the DOUT and DIN lines of the AD7715 together and connect them to the single data line of the processor. A 10 kΩ pull-up resistor should be used on this single data line. In this case, if the interface gets lost, because the read and write operations share the same line the procedure to reset it back to a known state is somewhat different than described previously. It requires a read operation of 24 serial clocks followed by a write operation where a Logic 1 is written for at least 32 serial clock cycles to ensure that the serial interface is back into a known state. DOUT SCLK CS DRDY MSB t5 t7 t8 t9 LSB t6 t3 t4 t10 Figure 8. Read Cycle Timing Diagram DIN SCLK CS MSB LSB t11 t12 t15 t16 t13 t14 Figure 9. Write Cycle Timing Diagram |
Similar Part No. - AD7715_17 |
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Similar Description - AD7715_17 |
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