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TSB41BA3 Datasheet(PDF) 2 Page - Texas Instruments |
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TSB41BA3 Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 63 page  TSB41BA3 IEEE 1394b THREEPORT CABLE TRANSCEIVER/ARBITER SLLS155A − MAY 2003 − REVISED OCTOBER 2003 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description The TSB41BA3 provides the digital and analog transceiver functions needed to implement a three-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB41BA3 is designed to interface with a link-layer controller (LLC), such as the TSB82AA2, TSB12LV21, TSB12LV26, TSB12LV32, TSB42AA4, TSB42AB4, TSB12LV01B, or TSB12LV01C. It may also be connected cable port to cable port to an integrated 1394 Link + PHY layer such as the TSB43AB2. The TSB41BA3 is powered by a single 3.3-V supply. The core voltage supply is supplied by an internal voltage regulator to the PLLVDD-1.8 and DVDD-1.8 terminals. To protect the phase-locked loop (PLL) from noise, the PLLVDD-1.8 terminals must be separately decoupled from the DVDD-1.8 terminals. The PLLVDD-1.8 terminals are decoupled with 1- µF and smaller decoupling capacitors, and the DVDD-1.8 terminals are separately decoupled with a 1- µF and smaller decoupling capacitors. The separation between DVDD-1.8 and PLLVDD-1.8 must be implemented by separate power supply rails or planes. The TSB41BA3 may be powered by dual supplies, a 3.3-V supply for I/O and a core voltage supply. The core voltage supply is supplied to the PLLVDD-1.8 and DVDD-1.8 terminals to the requirements in the recommended operating conditions section of this data sheet. The PLLVDD-1.8 terminals must be separated from the DVDD-1.8 terminals, the PLLVDD-1.8 terminals are decoupled with 1- µF and smaller decoupling capacitors, and the DVDD-1.8 terminals separately decoupled with 1- µF and smaller decoupling capacitors. The separation between DVDD-1.8 and PLLVDD-1.8 may be implemented by separate power supply rails, or by a single power supply rail, where the DVDD-1.8 and PLLVDD-1.8 are separated by a filter network to keep noise from the PLLVDD-1.8 supply. The TSB41BA3 requires an external 49.152-MHz crystal to generate a reference clock. The external clock drives an internal phase-locked loop (PLL), which generates the required reference signal. This reference signal provides the clock signals that control transmission of the outbound encoded information. A 49.152-MHz clock signal is supplied by the PHY to the associated LLC for synchronization of the two devices and is used for resynchronization of the received data when operating the PHY-link interface in compliance with the IEEE 1394a-2000 standard. A 98.304-MHz clock signal is supplied by the PHY to the associated LLC for synchronization of the two devices when operating the PHY-link interface in compliance with the IEEE 1394b-2002 standard. The power down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL. Data bits to be transmitted through the cable ports are received from the LLC on 2, 4, or 8 parallel paths (depending on the requested transmission speed and PHY-link interface mode of operation). They are latched internally, combined serially, encoded, and transmitted at 98.304, 122.78, 196.608, 245.76, 393.216, or 491.52 Mbits/s (referred to as S100, S100B, S200, S200B, S400, or S400B speed, respectively) as the outbound information stream. The PHY-link interface can follow either the IEEE 1394a-2000 protocol or the IEEE 1394b-2002 protocol. When using a 1394a-2000 LLC such as the TSB12LV26, the BMODE terminal must be deasserted. The PHY-link interface then operates in accordance with the legacy 1394a-2000 standard. When using a 1394b LLC such as the TSB82AA2, the BMODE terminal must be asserted. The PHY-link interface then conforms to the 1394b-2002 standard. The cable interface can follow either the IEEE 1394a-2000 protocol or the 1394b protocol on all ports. The mode of operation is determined by the interface capabilities of the ports being connected. When any of the three ports is connected to a 1394a-2000 compliant device, the cable interface on that port operates in the 1394a-2000 data-strobe mode at a compatible S100, S200, or S400 speed. When a bilingual port is connected to a 1394b compliant node, the cable interface on that port operates per the 1394b-2002 standard at S100B, S200B, or S400B speed. The TSB41BA3 automatically determines the correct cable interface connection method for the bilingual ports. |
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