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SNJ54LV166AW Datasheet(PDF) 6 Page - Texas Instruments |
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SNJ54LV166AW Datasheet(HTML) 6 Page - Texas Instruments |
6 / 15 page SN54LV166A, SN74LV166A 8BIT PARALLELLOAD SHIFT REGISTERS SCLS456B − FEBRUARY 2001 − REVISED DECEMBER 2004 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) TA = 25°C SN54LV166A SN74LV166A UNIT MIN MAX MIN MAX MIN MAX UNIT tw Pulse duration CLR low 8 9 9 ns tw Pulse duration CLK high or low 8.5 9 9 ns CLK INH before CLK ↑ 7 7 7 Data before CLK ↑ 6.5 8.5 8.5 tsu Setup time SH/LD before CLK ↑ 7 8.5 8.5 ns tsu Setup time SER before CLK ↑ 8.5 9.5 9.5 ns CLR ↑ inactive before CLK↑ 6 7 7 th Hold time Data after CLK ↑ −0.5 0 0 ns timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C SN54LV166A SN74LV166A UNIT MIN MAX MIN MAX MIN MAX UNIT tw Pulse duration CLR low 6 7 7 ns tw Pulse duration CLK high or low 6 7 7 ns CLK INH before CLK ↑ 5 5 5 Data before CLK ↑ 5 6 6 tsu Setup time SH/LD before CLK ↑ 5 6 6 ns tsu Setup time SER before CLK ↑ 5 6 6 ns CLR ↑ inactive before CLK↑ 4 4 4 th Hold time Data after CLK ↑ 0 0 0 ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C SN54LV166A SN74LV166A UNIT MIN MAX MIN MAX MIN4 MAX UNIT tw Pulse duration CLR low 5 5 5 ns tw Pulse duration CLK high or low 4 4 4 ns CLK INH before CLK ↑ 3.5 3.5 3.5 Data before CLK ↑ 4.5 4.5 4.5 tsu Setup time SH/LD before CLK ↑ 4 4 4 ns tsu Setup time SER before CLK ↑ 4 4 4 ns CLR ↑ inactive before CLK↑ 3.5 3.5 3.5 th Hold time Data after CLK ↑ 1 1 1 ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. |
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