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IDT74ALVCH162373 Datasheet(PDF) 1 Page - Integrated Device Technology

Part No. IDT74ALVCH162373
Description  3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND BUS-HOLD
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT74ALVCH162373 Datasheet(HTML) 1 Page - Integrated Device Technology

   
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INDUSTRIALTEMPERATURERANGE
IDT74ALVCH162373
3.3V CMOS16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
1
JANUARY 2004
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
© 2004 Integrated Device Technology, Inc.
DSC-4575/3
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
•VCC = 3.3V ± 0.3V, Normal Range
•VCC = 2.7V to 3.6V, Extended Range
•VCC = 2.5V ± 0.2V
• CMOS power levels (0.4
µµµµµ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
This16-bittransparentD-typelatchisbuiltusingadvanceddualmetalCMOS
technology.TheALVCH162373isparticularlysuitableforimple-mentingbuffer
registers,I/Oports,bidirectionalbusdrivers,andworkingregisters.Thisdevice
canbeusedastwo8-bitlatchesorone16-bitlatch.Whenthelatchenable(LE)
inputishigh,theQoutputsfollowthedata(D)inputs.WhenLEistakenlow,the
Q outputs are latched at the levels set up at the D inputs.
Abufferedoutput-enable(OE)canbeusedtoplacetheeightoutputsineither
anormallogicstate(highorlowlogiclevels)orahigh-impedancestate.Inthe
high-impedancestate,theoutputsneitherloadnordrivethebuslinessignifi-
cantly.Thehigh-impedancestateandtheincreaseddriveprovidethecapability
todrivebuslineswithoutneedforinterfaceorpullupcomponents.OEdoesnot
affectinternaloperationsofthelatch.Olddatacanberetainedornewdatacan
beeneteredwhiletheoutputsareinthehigh-impedancestate.
TheALVCH162373hasseriesresistorsinthedeviceoutputstructurewhich
will significantly reduce line noise when used with light loads. This driver has
been designed to drive ±12mA at the designated threshold levels.
The ALVCH162373 has “bus-hold” which retains the inputs’ last state
whenevertheinputgoestoahighimpedance.Thispreventsfloatinginputsand
eliminatestheneedforpull-up/downresistor.
DRIVE FEATURES:
• Balanced Output Drivers: ±12mA
• Low switching noise
IDT74ALVCH162373
3.3V CMOS 16-BIT TRANS-
PARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
AND BUS-HOLD
1
OE
C1
1D
1
D1
47
1
LE
1
Q 1
TO 7 OTHER CHANNELS
2
OE
2
D1
36
2
LE
2
Q 1
TO 7 O TH ER CHANNELS
1
48
2
24
25
13
C1
1D
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems


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