AD73360ASUZ datasheet(16/36 Pages) AD

Part #	AD73360ASUZ

Description	Six-input Channel Analog Front End

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REV.

B

AD73360

–15–

Table VII. Control Register A Description

7

654321

0

RESET

DC2

DC1

DC0

SLB

–

MM

DATA/

PGM

Bit Name

Description

0

DATA/

PGM

Operating Mode (0 = Program; 1 = Data Mode)

1

MM

Mixed Mode (0 = OFF; 1 = Enabled)

2

Reserved

Must Be Programmed to Zero (0)

3

SLB

SPORT Loop-Back Mode (0 = OFF; 1 = Enabled)

4

DC0

Device Count (Bit 0)

5

DC1

Device Count (Bit 1)

6

DC2

Device Count (Bit 2)

7

RESET

Software Reset (0 = OFF; 1 = Initiates Reset)

Table VIII. Control Register B Description

76543210

C E E

MCD2

MCD1

MCD0

SCD1

SCD0

DR1

DR0

Bit Name

Description

0

DR0

Decimation Rate (Bit 0)

1

DR1

Decimation Rate (Bit 1)

2

SCD0

Serial Clock Divider (Bit 0)

3

SCD1

Serial Clock Divider (Bit 1)

4

MCD0

Master Clock Divider (Bit 0)

5

MCD1

Master Clock Divider (Bit 1)

6

MCD2

Master Clock Divider (Bit 2)

7

CEE

Control Echo Enable (0 = OFF; 1 = Enabled)

Table IX. Control Register C Description

76543210

5VEN

RU

PUREF

––––

GPU

Bit Name

Description

0

GPU

Global Power-Up Device (0 = Power Down; 1 = Power Up)

1

Reserved

Must Be Programmed to Zero (0)

2

Reserved

Must Be Programmed to Zero (0)

3

Reserved

Must Be Programmed to Zero (0)

4

Reserved

Must Be Programmed to Zero (0)

5

PUREF

REF Power (0 = Power Down; 1 = Power Up)

6

RU

REFOUT Use (0 = Disable REFOUT; 1 = Enable REFOUT)

7

5VEN

Enable 5 V Operating Mode (0 = Disable 5 V Mode;

1 = Enable 5 V Mode)

CONTROL REGISTER A

CONTROL REGISTER B

CONTROL REGISTER C

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