AD7729

–15–

REV. 0

ADSP-21xx

DR

RFS

SCLK

TFS

DT

AD7729

SDO

SDOFS

SCLK

SDIFS

SDI

Figure 21. AD7729 to ADSP-21xx Interface

AD7729-to-TMS320C5x Interface

Figure 22 shows the interface between the AD7729 and the

TMS320C5x DSP. The TMS320C5x is configured as follows:

MCM = 0 (CLKX is an input), TXM = 1 (the transmit frame

sync signal is generated by the DSP), FSM = 1 (a frame sync is

required for each transfer), FO = 0 (16-bit word length).

TMS320C5x

DR

FSR

CLKX

FSX

DX

AD7729

SDO

SDOFS

SCLK

SDIFS

SDI

CLKR

Figure 22. AD7729 to TMS320C5x Interface

Power-Down

Each section of the AD7729 can be powered down. The Rx

ADCs and the auxiliary DAC can be powered down individually

by setting the appropriate bits in the control registers. When

each section is powered up, time must be allowed so that the

analog and digital circuitry can settle and, also, time is needed

for the reference REFCAP to power up. To reduce this power-

up time, Bit LP can be set to 1 so that when the ADCs and

DAC are powered down, the reference REFCAP remains pow-

ered up by setting Bit LP to 1. Therefore, because the reference

is powered up, the time needed for circuitry to settle when a

section is powered up is reduced considerably since the refer-

ence does not require time to power up and settle.

When all sections of the AD7729 are powered down, including

the reference, the MCLK is stopped after 64 clock periods fol-

lowing the detection of the low power state. The MCLK reacti-

vates when the AD7729 is communicated with, i.e., the SPORTs

are activated, RxON is taken high, etc.

Grounding and Layout

Since the analog inputs to the AD7729 are differential, most of

the voltages in the analog modulator are common-mode volt-

ages. The excellent Common-Mode Rejection of the part will

remove common-mode noise on these inputs. The analog and

digital supplies of the AD7729 are independent and separately

pinned out to minimize coupling between analog and digital

sections of the device. The digital filters following the ADCs will

provide rejection of broadband noise on the power supplies,

except at integer multiples of the modulator sampling frequency.

The digital filters also remove noise from the analog inputs

provided the noise source does not saturate the analog modula-

tor. However, because the resolution of the AD7729 ADCs is

high and the noise levels from the AD7729 are so low, care

must be taken with regard to grounding and layout.

The printed circuit board that houses the AD7729 should be

designed so that the analog and digital sections are separated

and confined to certain sections of the board. This facilitates the

use of ground planes that can be easily separated. A minimum

etch technique is generally best for ground planes as it gives the

best shielding. Digital and analog ground planes should only be

joined in one place. If the AD7729 is the only device requiring

an AGND-to-DGND connection, the ground planes should be

connected at the AGND-and-DGND pins of the AD7729. If

the AD7729 is in a system where multiple devices require AGND-

to-DGND connections, the connection should still be made at

one point only, a star ground point that should be established as

close as possible to the AD7729.

Avoid running digital lines under the device as these will couple

noise onto the die. The analog ground plane should be allowed

to run under the AD7729 to avoid noise coupling. The power

supply lines to the AD7729 should use as large a trace as pos-

sible to provide low impedance paths and reduce the effects of

glitches on the power supply lines. Fast switching signals like

clocks should be shielded with digital ground to avoid radiating

noise to other sections of the board and clock signals should

never be run near the analog inputs. Traces on opposite sides of

the board should run at right angles to each other. This will

reduce the effects of feedthrough through the board. A microstrip

technique is by far the best but is not always possible with a

double-sided board. In this technique, the component side of

the board is dedicated to ground planes while signals are placed

on the other side.

Good decoupling is important when using high speed devices.

All analog and digital supplies should be decoupled to AGND

and DGND respectively with 0.1

µF ceramic capacitors in paral-

lel with 10

µF tantalum capacitors. To achieve the best from

these decoupling capacitors, they should be placed as close as

possible to the device, ideally right up against the device. In

systems where a common supply voltage is used to drive both

the AVDD and DVDD of the AD7729, it is recommended that

the system’s AVDD supply be used. This supply should have

the recommended analog supply decoupling between the AVDD

pins of the AD7729 and AGND and the recommended digital

supply decoupling capacitors between the DVDD pins and

DGND.